Controlled collapse chip connection (C4) integrated circuit...

Details Controlled collapse chip connection (C4) integrated circuit... Controlled collapse chip connection (C4) integrated circuit...

1999-03-03

2001-05-29

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S064000, C438S117000

Reexamination Certificate

active

06238948

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit package.
2. Background Information
Integrated circuits are typically assembled into a package that is soldered to a printed circuit board.
FIG. 1
shows a type of integrated circuit package that is commonly referred to as flip chip or C
4
package. The integrated circuit
1
contains a number of solder bumps
2
that are soldered to a top surface of a substrate
3
.
The substrate
3
is typically constructed from a composite material which has a coefficient of thermal expansion that is different than the coefficient of thermal expansion for the integrated circuit. Any variation in the temperature of the package may cause a resultant differential expansion between the integrated circuit
1
and the substrate
3
. The differential expansion may induce stresses that can crack the solder bumps
2
. The solder bumps
2
carry electrical current between the integrated circuit
1
and the substrate
3
so that any crack in the bumps
2
may affect the operation of the circuit
1
.
The package may include an underfill material
4
that is located between the integrated circuit
1
and the substrate
3
. The underfill material
4
is typically an epoxy which strengthens the solder joint reliability and the thermo-mechanical moisture stability of the IC package.
The package may have hundreds of solder bumps
2
arranged in a two dimensional array across the bottom of the integrated circuit
1
. The epoxy
4
is typically applied to the solder bump interface by dispensing a single line of uncured epoxy material along one side of the integrated circuit. The epoxy then flows between the solder bumps. The epoxy
4
must be dispensed in a manner that covers all of the solder bumps
2
.
It is desirable to dispense the epoxy
4
at only one side of the integrated circuit to insure that air voids are not formed in the underfill. Air voids weaken the structural integrity of the integrated circuit/substrate interface. Additionally, the underfill material
4
must have good adhesion strength with both the substrate
3
and the integrated circuit
1
to prevent delamination during thermal and moisture loading. The epoxy
4
must therefore be a material which is provided in a state that can flow under the entire integrated circuit/substrate interface while having good adhesion properties.
The substrate
3
is typically constructed from a ceramic material. Ceramic materials are relatively expensive to produce in mass quantities. It would therefore be desirable to provide an organic substrate for a C
4
package. Organic substrates tend to absorb moisture which may be released during the underfill process. The release of moisture during the underfill process may create voids in the underfill material. Organic substrates also tend to have a higher coefficient of thermal expansion compared to ceramic substrates that may result in higher stresses in the die, underfill and solder bumps. The higher stresses in the epoxy may lead to cracks during thermal loading which propagate into the substrate and cause the package to fail by breaking metal traces. The higher stresses may also lead to die failure during thermal loading and increase the sensitivity to air and moisture voiding. The bumps may extrude into the voids during thermal loading, particularly for packages with a relatively high bump density. It would be desirable to provide a C
4
package that utilizes an organic substrate.
SUMMARY OF THE INVENTION
One embodiment of the present invention is an integrated circuit package which may include an integrated circuit that is mounted to a substrate. The package may include an underfill material that is attached to the integrated circuit and the substrate and a fillet which seals the underfill material.


REFERENCES:
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patent: 5919329 (1998-10-01), Banks et al.
patent: 5998242 (1999-12-01), Kirkpatrick et al.
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patent: 02056941 (1990-02-01), None
patent: 03041146 (1992-02-01), None
patent: 08153830 (1996-06-01), None
International Search Report, PCT/US 00/03813, Feb. 14, 2000.
XP-000912270 “High Reliability Underfill for Flip-Chip Application”, Materials Research Society Symposium Proceedings, Sumita et al., 1997.

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