Controlled CMOS substrate voltage generator

Details Controlled CMOS substrate voltage generator Controlled CMOS substrate voltage generator

1987-11-13

1989-06-27

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072965, 3073032, 307304, 307246, 357 236, 357 42, 357 52, H03K 301, H03K 3335, H03K 1756, H03L 2978

Patent

active

048432563

ABSTRACT:
A controlled CMOS substrate voltage generator generates a rectangular wave pulse which is supplied to the pumping circuit by a pumping capacitor and controlled decoupling members. At the same time the decoupling members are activated by a control circuit and are completely opened, so that the full pumping lift is completely utilized without reduction due to threshold voltages. In order to reduce the injection of charge carriers of nCMOS decoupling members, inversely activated pMOS decoupling members, which are strongly conducting at low substrate bias voltage near 0V, are connected in parallel to the latter. To increase performance, the circuit is designed as a circuit in phase opposition. Improved sensors are provided, which during the active phase maintain the shift of the substrate voltage produced upon wobble of the bit strings toward more negative values by alternation of the reference voltage of the sensor.

REFERENCES:
patent: 3794862 (1974-02-01), Jenne
patent: 4336466 (1982-06-01), Sud et al.
patent: 4591738 (1986-05-01), Bialas, Jr. et al.
patent: 4636658 (1987-01-01), Arakawa
patent: 4670669 (1987-06-01), Cottrell et al.
patent: 4695746 (1987-09-01), Tobita

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