Controlled bit line discharge for channel erases in...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185220, C365S185240, C365S185250, C365S185290

Reexamination Certificate

active

07808827

ABSTRACT:
Systems and/or methods that facilitate discharging bit lines (BL) associated with memory arrays in nonvolatile memory at a controlled rate are presented. A discharge component facilitates discharging the BL at a desired rate thus preventing the “hot switching” phenomenon from occurring within a y-decoder component(s) associated with the nonvolatile memory. The discharge component can be comprised of, in part, a discharge transistor component that controls the rate of BL discharge wherein the gate voltage of the discharge transistor component can be controlled by a discharge controller component. The rate of BL discharge can be determined by the size of discharge transistor component used in the design, the strength and/or size of the y-decoder component, the number of erase errors that occur for a particular memory device, and/or other factors in order to facilitate preventing hot switching from occurring.

REFERENCES:
patent: 3765002 (1973-10-01), Basse
patent: 6667910 (2003-12-01), Abedifard et al.
patent: 7160773 (2007-01-01), Randolph
patent: 2006/0104122 (2006-05-01), Choy

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