Active solid-state devices (e.g. – transistors – solid-state diode – Responsive to non-electrical signal – Temperature
Patent
1991-11-27
1993-08-03
Mintel, William
Active solid-state devices (e.g., transistors, solid-state diode
Responsive to non-electrical signal
Temperature
257497, 257498, 257551, 257570, 257603, 257606, H01L 2990
Patent
active
052332144
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The invention relates to a controllable, temperature-compensated voltage limiter.
BACKGROUND
It is known to employ so-called punch-through diodes for temperature-controlled voltage reference or voltage limitation. Punch-through diodes are p.sup.+ np.sup.+ or n+pn+semiconductor structures in which the width and doping of the central zone is selected such that no avalanche or Zener effect appears when voltage is applied to the two outer layers. If the voltage is increased, the space-charge region of the blocking pn-junction expands until it touches the pn-junction on the opposite side. This pn-junction operated in the on-state injects charge carriers into the field of the space-charge region, so that the current sharply increases starting at this voltage. At least with certain current densities, the current-voltage characteristic curve is practically independent of the temperature.
However, in connection with such punch-through diodes it is disadvantageous that the limiting voltage increases with the square of the width of the central highly resistive layer. Because of fluctuations in the penetration depth of the p-diffusion occurring during the manufacturing process it is difficult to specifically produce punch-through diodes with exactly defined breakdown values and to integrate them in particular for voltage limitation into planar transistors.
SUMMARY OF THE INVENTION
By means of the step in accordance with the invention, where the voltage to be limited is applied to the blocking pn-junction of the punch-through diode and additionally an adjustable auxiliary voltage is applied across the other pn-junction, it is achieved that the punch-through voltage can be increased corresponding to the auxiliary voltage. Based on the possibility of adjustment, it is possible to set defined breakdown values independent of the fluctuations of the penetration depth of the p-diffusion occurring during the manufacturing process. In this way such punch-through diodes, wired in accordance with the invention, are suitable for a plurality of uses in which temperature-compensated, exactly defined breakdown values are important. The invention can be employed with planar and non-planar components.
The required auxiliary voltage can be provided by an independent voltage source as well as by a settable or adjustable potentiometer.
The punch-through diode equipped in accordance with the invention can be integrated into transistors, particularly Darlington transistors, and thus is particularly suitable for the base-collector clamping in ignition transistors of an ignition system for motor vehicles.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention will be described in detail by means of the drawings.
FIG. 1 is a representation in principle of a punch-through diode arrangement in the form of a p.sup.+ np.sup.+ p arrangement,
FIG. 2 is a representation where a punch-through diode is integrated with a p-ring into the base-collector path of a planar transistor for controllable voltage limitation,
FIG. 3 is a diagram into which the blocking-state voltage U.sub.CEO has been entered as a function of the auxiliary voltage U.sub.H for a fixed current I.sub.C =500 .mu.A of a test construction for temperatures -40.degree. C., 25.degree. C. and 75.degree. C.,
FIG. 4 is a circuit arrangement for generating an auxiliary voltage U.sub.H via a potentiometer,
FIG. 5 is a diagram showing the blocking-state voltage U.sub.CEO as a function of the potentiometer resistance R.sub.1 (R.sub.2 =500 kOhm) for temperatures -40.degree. C., 25.degree. C. and 75.degree. C.,
FIG. 6 is a sectional view through a punch-through diode arrangement for displacement of the punch-through zone into the depth of the semiconductor .
DETAILED DESCRIPTION
A p.sup.+ np.sup.+ punch-through structure arrangement is shown in FIG. 1. Two p-zones 2, 3 have been diffused into an n-doped semiconductor crystal 1. The distance between the p-zones 2, 3 is W1. Doping of the zone 1 and the width W1 have been selected in such a way that no avalanche or Zener
REFERENCES:
patent: 3787717 (1974-01-01), Fischer et al.
patent: 4262295 (1981-04-01), Okano et al.
patent: 4554568 (1985-11-01), Champon et al.
patent: 4870467 (1989-09-01), Boland et al.
patent: 4994874 (1991-02-01), Shimizu et al.
de Cogan, "The Punch-Through Diode," Microelectronics, vol. 8, No. 2, 1977, pp. 20-23.
Goto, Patent Abstracts of Japan, vol. 10, No. 192 [E-417] [2248].
Hayashi, Patent Abstracts of Japan, vol. 11, No. 17 [E-471,2464].
Gorlach Alfred
Meinders Horst
Mintel William
Robert & Bosch GmbH
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