Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
1999-10-04
2001-09-04
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S077000, C257S256000, C257S268000, C257S279000, C257S280000
Reexamination Certificate
active
06285046
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a controllable semiconductor structure having improved switching properties.
The literature describes numerous component structures referred to as JFET or MESFET, in which the conduction properties are controlled by the voltage-dependent expansion of one or more space-charge zones (pn transition in JFET, Schottky transition in MESFET). The base structure was first proposed by W. Schockley: A Unipolar ‘Field-Effect’ Transistor, in the Proceedings of the I.R.E.,
1952
. In standard-technology conversions, as are described in W. von Münch, Einfuhrung in die Halbleitertechnologie [Introduction to Semiconductor Technology], Teubner, 1993, large parasitic capacitances (especially input capacitance and reverse-transfer or Miller capacitance) occur, leading to low limit frequencies in amplifiers and causing long switching times, and therefore large switching losses, in switching applications. This is also the case for high-blocking JFETs that operate according to the RESURF principle, for example, as described in U.S. Pat. No. 4,422,089; in these JFETs, the field-intensity peaks at the component surface are reduced by a suitable selection of the doping and depth of the lateral drift zone.
It is known from textbooks, e.g., R. Paul: Elektronische Halbleiterbauelemente [Electronic Semiconductor Components] that JFETs and MESFETs are usually produced on, for example, insulating, semiinsulating or insulated substrates (e.g., the SOI technique or sapphire in silicon, highly-compensated material in gallium arsenide, etc.) to minimize the parasitic capacitances.
These techniques have the following disadvantages:
1) Because of the insulating, semi-insulating or insulated substrate, no current flow can occur in the vertical direction. Therefore, no vertical components can be produced with this method, which limits its use for power components.
2) The production of wafers with an insulating or insulated substrate is complicated and expensive. In addition, problems due to, for example, temperature limitations can occur in the further processing.
3) In semiconductors that cannot be rendered semi-insulating through compensation, a second material must be used as an insulator. This leads to, on the one hand, stress because of different thermal expansion coefficients and, on the other hand, more intense internal heating of the components because of the generally lower thermal conductivity of the insulator. Furthermore, the crystal quality of the active semiconductor layer is frequently worse in heteroepitaxial production on an insulator than in homoepitaxially-produced layers because of erroneous lattice adaptation.
4) The insulation technique can only be combined with the RESURF technique in thin insulator layers, which in turn increases the parasitic capacitances.
It is therefore the object of the invention to use simple technological measures and few steps to create a semiconductor structure that has a good blocking effect, and permits higher limit frequencies and lower switching losses than conventional components.
SUMMARY OF THE INVENTION
The above object generally is achieved according to the present invention by a controllable semiconductor structure having a base region, a source region and a drain region, with a conductive channel being provided in the base region between the source and the drain, and wherein the channel can be pinched off by zones parallel thereto, including an active control zone and an oppositely-located passive control zone, which respectively form a blockable transition to the base region; a conductive connection is provided between the passive control zone and the source region; and the semiconductor material of the base region has a band gap of more than 1.2 eV.
The drawing illustrates embodiments of the invention.
REFERENCES:
patent: 59-65486 (1984-04-01), None
Kaminski Nando
Neubrand Horst
Daimler-Chrysler AG
Kunitz Norman N.
Loke Steven
Venable
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