Controllable attenuator

Details Controllable attenuator Controllable attenuator

2002-08-28

2004-01-27

Young, Brian (Department: 2817)

Wave transmission lines and networks

Attenuators

C330S284000, C327S308000

Reexamination Certificate

active

06683511

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
The present application claims priority to currently pending United Kingdom Patent Application number 0121140.8, filed on Aug. 30, 2001.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
BACKGROUND OF THE INVENTION
The present subject matter generally relates to a controllable attenuator for use in radio receivers and other electronic devices.
A controllable attenuator is often incorporated before a low noise amplifier (LNA) in the signal path of a radio receiver. Controllable attenuators may also be known as switchable or programmable attenuators. The usual effect of the attenuator is to improve the linearity characteristics and power handling capability of the receiver without increasing the noise figure or reducing the gain when the signal-to-noise figure ratio (SNR) is sufficiently high to be sacrificed without loss of information. One such attenuator is described in U.S. Pat. No. 6,147,568 and is shown schematically in FIG.
1
.
Referring to
FIG. 1
, the attenuator
10
comprises a pair of bipolar, npn, transistors Q
1
and Q
2
which have their emitter/collector paths connected in reverse parallel between a point
1
in the radio-frequency signal input path and the signal return path G (shown as ground potential). A bias voltage is applied to the point
1
in the signal input path and thus to the interconnected collector electrode of transistor Q
1
and emitter electrode of transistor Q
2
by way of a high value resistor R
2
from a voltage source Vr. The base electrodes of the transistors Q
1
and Q
2
are arranged to be biased individually by means of a bias control circuit
3
. The point
1
in the input signal path is connected to the input of a low noise amplifier
2
by way of a coupling capacitor C
1
.
The transistors Q
1
, Q
2
, the control circuit
3
, the capacitor C
1
and the amplifier
2
may all be provided on an integrated circuit chip
4
in the radio-frequency signal path.
When the bias currents supplied by the control circuit
3
are zero, both transistors Q
1
and Q
2
are non-conducting, and the radio-frequency input signal is passed to the amplifier
2
without attenuation. When bias currents are supplied by the circuit
3
, both the transistors Q
1
and Q
2
are saturated, and their small dynamic output impedance shunts the input signal to ground. The actual attenuation achieved depends upon the value of the shunt impedance.
The attenuator has two modes of operation: pre-set and variable. In the pre-set mode, the base bias currents are switched between zero and the respective values which provide the required pre-set value of attenuation. In the variable attenuation mode, the bias currents are varied either in steps or continuously to achieve the required attenuation variation.
Since the attenuator when switched off is not the source of any significant noise power, the transistors Q
1
and Q
2
each have as small an emitter area as possible for the required maximum attenuation, in order to limit noise flow from the substrate and the parasitic resistors (not shown). In this condition, the bias from the source Vr biases the junctions of the collector/base of Q
1
and the emitter/base of Q
2
to decrease the junction capacitances. The maximum value of this reverse bias voltage is limited by the maximum safe reverse voltage for the emitter/base junction of the transistor Q
2
. The value of the resistor R
2
should be on the order of 10 k&OHgr; or more to minimize its noise contribution.
When the attenuator is switched on, it is required to be very linear. Hence the two transistors Q
1
and Q
2
are in reverse parallel. The reverse parallel connection of the transistors Q
1
and Q
2
ensures that one of them is always in the “normal” sense of operation, while the other is operating in the inverse sense for any given polarity of radio-frequency input signal, making their combined dynamic output impedances much more linear over the range of voltages of interest.
The bases of the transistors Q
1
and Q
2
are biased independently because the transistor operating in the inverse sense has a lower input impedance and might “steal” the majority of the bias current if the bases were connected. The output impedance of the two transistors in parallel remains linear over at least + or −100 mV across the collector-emitter paths, and the shunting current can be as high as the bias current multiplied by the forward beta. This produces linear attenuation for input signal powers up to 3-10 dBm depending on the value of attenuation. The maximum input power can be increased if a small value resistor R
3
is connected in series between the point
1
and the interconnected collector and emitter electrodes of the transistors Q
1
, Q
2
respectively. This also improves the linearity of the attenuator
10
but, for the same maximum level of attenuation, the emitter and collector areas of the transistors Q
1
and Q
2
must be increased, together with the bias currents. At high frequencies, these larger areas result in higher noise flow from the substrate and the parasitic resistors.
For extending the range of attenuation it is possible to connect two or more attenuators
10
in parallel.
The
FIG. 1
attenuator has the disadvantage that the input impedance of the receiver is dependent on the attenuation provided by the attenuator, which may cause matching problems.
A PIN diode attenuator, such as that described in “Reducing IM Distortion in CDMA Cellular”, by Dick Bain,
RF Design
, December 1997, pages 46-53, requires a separate matching circuit, which occupies a large area on the printed board of the receiver. A gain controlled LNA, such as that disclosed in “A Direct Conversion Receiver for 900 MHz (ISM Band) Spead-Spectrum Digital Cordless Telephone”, by Hull et al IEEE J. Solid-State Circuits, Vol. 31, No. 12, 1996, pages 1955-1963, can be integrated onto the receiver chip, but does not show improvements in linearity characteristics and power handling in direct proportion to the levels of attenuation.
OBJECTS AND SUMMARY OF THE INVENTION
Objects and advantages of the invention will be set forth in part in the following description, or may be obvious from the description, or may be learned through practice of the invention.
In accordance with aspects of the disclosed technology, it is an object of exemplary embodiments of the present subject matter to provide a controllable attenuator with improved linearity.
It is a further object of exemplary embodiments of the disclosed technology to provide a controllable attenuator that operates in multiple states and that maintains a generally stable input impedance independent of the operating states of the attenuator.
An exemplary embodiment of the present subject matter may correspond to a controllable attenuator having an input and an output. Such attenuator may preferably include a first resistive element and a first capacitor connected in series between the input and the output, a first controllable shunting transistor connected between the output and a supply terminal via a second resistive element, and a controllable bypass transistor connected between the input and the output.
Such exemplary controllable attenuator may further comprise a first controllable series transistor connected in series with the first resistive element, wherein the first series transistor is arranged to be switched in conjunction with the first shunting transistor.
Such exemplary controllable attenuator may further comprise a third resistive element and a second controllable series transistor connected in series between the input and the output, and a second controllable shunting transistor connected between the output and the supply terminal via a third resistive element. Such second series transistor is preferably arranged to be switched in conjunction with the second shunting transistor.
Exemplary controllable attenuator embodiments in accordance with the present subject matter may also include a second capacitor connected between the output and the first shunting transistor. Still f

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