Control unit with digital addressing memory for a DC-to-AC inver

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Details

363 41, 363 42, 363 96, 363136, H02P 1320, H02M 108

Patent

active

044660707

ABSTRACT:
A control unit for DC-to-AC inverter having an addressing memory which is loaded with an addressing table by a microprocessor for a respective frequency range of the inverter output voltage. In the addressing table, a predetermined portion of information is provided for each addressing combination of the switches of the DC-to-AC inverter, the portion of information containing the addressing combination itself and the number of clock pulses for which the addressing combination will be present. The portions of information are interrogated at different speeds depending upon the desired inverter output frequency. A frequency divider is addressed by a clock generator, the frequency divider receiving a division factor from the memory, the division factor being inversely proportional to the desired DC-to-AC inverter output frequency. The output signal of the divider decrements a counter which is loaded with a number of clock pulses associated with the respective addressing combination. Upon achieving a zero count, a new portion of information of the addressing table is provided at the output of the memory.

REFERENCES:
patent: 4267570 (1981-05-01), Braun
patent: 4290108 (1981-09-01), Woehrle et al.
patent: 4370702 (1983-12-01), Shuey et al.

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