Control unit of input-output interface circuits in an electronic

Details Control unit of input-output interface circuits in an electronic Control unit of input-output interface circuits in an electronic

1982-10-14

1988-12-13

Shaw, Gareth D.

Boots, shoes, and leggings

3408255, G06F 946

Patent

active

047915536

ABSTRACT:
The control unit is arranged to handle the requests for transmission and reception interrupts (i.e. requests to the central logic unit CPU to halt its operative program in order to transmit or receive messages to or from a peripheral unit) in arrival from the input/output interface circuits, each of which is associated with a peripheral unit. To this purpose, the interface circuits are cyclically scanned to groups of n: the presence of at least one interrupt request halts the scanning and causes a request criterion to be transmitted to the central logic unit (CPU) by the control unit. The address of the peripheral unit presenting the highest priority among those of the group requiring an interrupt is written into the state register of the control unit, the address being composed of the number of the group (supplied by the scanner) and by the code generated by a priority coder. The transmission interrupts are handled separately from the reception interrupts; the DMA transfer requests (Direct Memory Access), handled by another circuit, have priority with respect to the interrupts and halt the scanning for a time slot strictly necessary to guarantee a correct transmission in the DMA transfer. The control unit is able to display and not to execute interrupt requests generated by peripheral units disabled by CPU or in case of faulty or missing peripheral units.

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