Control unit for a functional processor

Details Control unit for a functional processor Control unit for a functional processor

1981-12-07

1984-05-22

Smith, Jerry

Boots, shoes, and leggings

G06F 922, G06F 928

Patent

active

044505256

ABSTRACT:
A control unit for a functional processor is disclosed which minimizes programming complexity by eliminating data transfers and the transfer control associated with two level memory systems and which improves flexibility in program task changeovers in pipelined arithmetic architectures. This is accomplished by employing common page addressing for accessing memory address stacks for storing either main memory addresses or address increments, coefficient address stacks for storing coefficient memory addresses or address increments, and microinstruction sequencing control branch stacks for storing branch and loop control parameters. This permits chaining of long sequences of signal processing subroutines without external control and the associated execution time overhead. An additional feature is a revolving buffer operation in which a plurality of main memory modules are cyclically connected to each of a plurality of scratch pad buffers in the arithmetic unit in a synchronous manner so as to maximize the throughput of the combined operation of memory transfers, arithmetic processing and I/O transfers. In another feature, the controller employs a dual clocking arrangement whereby scratch pad storage elements and arithmetic elements can be selectively controlled to operate at twice the rate at which microinstructions are accessed from the microprogram store. The resulting controller for a pipelined arithmetic architecture provides a closely coupled control of looping and branching control operations with storage accessing operations and pipelined arithmetic operations to provide for immediate and flexible responses to changes in programming tasks.

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