Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2005-11-29
2005-11-29
Eisen, Alexander (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C359S223100
Reexamination Certificate
active
06970150
ABSTRACT:
A spatial light modulator clocking method, called fast-clear, which employs embedded clear hardware in the SLM to enable the fast-clear bit to generate least-significant short-bit periods and without any bit ordering restrictions. In this method, fast data clears34are inserted between block data loads32,36within a frame refresh period. This method virtually eliminates the artifacts associated with the earlier reset-release timing method without the bit-ordering restriction of the jog-clear method.
REFERENCES:
patent: 6201521 (2001-03-01), Doherty
patent: 0 772 181 (1997-05-01), None
patent: 0 841 815 (1998-05-01), None
U.S. Appl. No. 09/918,837, filed Jul. 21, 2001, Doherty et al.
Doherty Donald B.
Hewlett Gregory J.
Brady III Wade James
Brill Charles A.
Eisen Alexander
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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