Control system having reduced response time

Television – Synchronization – Automatic phase or frequency control

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Details

348707, 327156, 327337, 327344, 331 17, A04N 550

Patent

active

057643008

ABSTRACT:
A more rapid charging of an integrating capacitor of a PLL is provided when large frequency changes are desired. In one embodiment, the phase locked loop (PLL) circuit sinks or sources current to charge or discharge the integrating capacitor. A threshold voltage proportional to a current through the capacitor turns on a circuit which sinks or sources more current of the proper polarity to the integrating capacitor from an external source until a PLL lock is achieved. Once the lock is achieved, if a small correction current is required by the PLL, the small correction current is below a threshold required to actuate the augmenting circuit, and the PLL loop behaves in the usual manner as if the augmenting circuit were not present. In another embodiment, the integrating capacitor is reduced in value by switchably connecting a second capacitor in series with the integrating capacitor so that the total reduced capacitance of reduced value can be charged more quickly.

REFERENCES:
patent: 3064215 (1962-11-01), Tulgan et al.
patent: 3389346 (1968-06-01), Hoffmann
patent: 4053933 (1977-10-01), Collins
patent: 4327329 (1982-04-01), Papworth
patent: 4937536 (1990-06-01), Reinhardt et al.
patent: 5343169 (1994-08-01), Debaty
New Phase-Lock Loop Circuit Providing Very Fast Acquisition Tim, by Bernard S. Glance, published in the IEEE Transactions on Microwave Theory, Vo. MTT-33, No. 9, Sep.1985.
Simple Switching Technique for Fast PLL Frequency Synthesisers, by M.J. Underhill and R.I.H. Scott, Electronic Letters, Jun. 11, 1981, vol. 17, No. 12.
Underhill et al., "Simple Switching Technique for Fast PLL Frequency Synthesizers", Jun. 11, 1981, vol.17, No.12, pp. 405-406.

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