Control system for vector processor with serialization instructi

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3642318, 36423221, G06F 15347, G06F 938

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active

050601482

ABSTRACT:
An access instruction pipeline for receiving an access instruction for accessing data to be inputted to the pipeline of a vector processor includes a plurality of buffers for buffering a memory request and sending it to a storage control unit, and a detector for judging at the last stage of the plurality of buffers if an instruction is an access instruction or a serialization instruction for serializing the memory access instructions among access instruction pipelines. If a serialization instruction is detected at the last stage of a pipeline, the pipelining operation is stopped, but instructions are filled up in the stopped pipeline. After a serialization instruction has been detected at the last stage of all the pipeline, a pipelining operation starts again.

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Fujitsu Scientific Tech. J., Mar. 1985, No. 1, vol. 21, "The Super Computer FACOM VP System", by Tsmura et al., pp. 90-108.

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