Control signal generator for processing a video signal

Details Control signal generator for processing a video signal Control signal generator for processing a video signal

1989-03-14

1991-03-26

Shepperd, John W.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358139, 358148, H04N 514

Patent

active

050033930

ABSTRACT:
The described control signal generator for processing a video signal is characterized by an addressable memory (PR1) whose addresses are associated with equally long time intervals of a video picture. The binary coded amplitude is stored at an address of the memory (PR1), which amplitude is to be assumed by the control signal (SS) generated by the control signal generator in the associated time interval. A counting unit (Z) which is clocked by a counter clock pulse (T) successively generates the addresses corresponding to consecutive time intervals of a video picture and being applied to the address inputs of the addressable memory (PR1). The frequency of the counter clock pulse (T) is chosen to be such that all addresses associated with a video picture are traversed during the time length of a video picture. A feedback between the output of the addressable memory (PR1) and the counting unit (Z) sets the counting unit (Z) at the address of the last time interval of a video picture to the address of the first time interval of the next video picture.

REFERENCES:
patent: 4408337 (1983-10-01), Cang
patent: 4625241 (1986-11-01), Ohzeki
patent: 4631586 (1986-12-01), Gennetten et al.
patent: 4825285 (1989-04-01), Speidel et al.
patent: 4855826 (1989-08-01), Wischermann et al.
patent: 4864400 (1989-09-01), Kumada et al.

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