Control signal generation for a low jitter...

Details Control signal generation for a low jitter... Control signal generation for a low jitter...

2007-05-01

2007-05-01

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S147000, C327S007000, C327S012000

Reexamination Certificate

active

11260097

ABSTRACT:
A phase detector and control signal generator responds to a reference signal and a feedback signal to produce a non-delayed up and down signal. A programmable delay unit delays the non-delayed up and down signal to provide up and down signals for a charge pump. A divider configured to respond to the up and down signals provides a divided clock signal. A non-overlapped clock generator configured to respond to the divided clock signal to provide non-overlapped hold even and hold odd signals for the switched-capacitor ripple-smoothing filter.

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Maxim, Adrian. “A Low-Jitter 125-1250 MHz Process-Independent And Ripple-Poleless O.18um CMOS PLL Based On A Sample-Reset Loop Filter,”.
IEEE Journal of Solid-State Circuits, vol. 36, No. 11, Nov. 2001.
U.S. Appl. No. 10/841,987, filed May 7, 2004, Zhu.

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