Control signal generation for a low jitter...

Details Control signal generation for a low jitter... Control signal generation for a low jitter...

2006-02-21

2006-02-21

Lam, Tuan T. (Department: 2816)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C327S007000, C327S012000

Reexamination Certificate

active

07002418

ABSTRACT:
A phase detector and control signal generator responds to a reference signal and a feedback signal to produce a non-delayed up and down signal. A programmable delay unit delays the non-delayed up and down signal to provide up and down signals for a charge pump. A divider configured to respond to the up and down signals provides a divided clock signal. A non-overlapped clock generator configured to respond to the divided clock signal to provide non-overlapped hold even and hold odd signals for the switched-capacitor ripple-smoothing filter.

REFERENCES:
patent: 4751469 (1988-06-01), Nakagawa et al.
patent: 5373255 (1994-12-01), Bray et al.
patent: 6100721 (2000-08-01), Durec et al.
“A Low-Jitter 125-1250-MHz Process-Independent And Ripple-Poleless 0.18-μm CMOS PLL Based On A Sample-Reset Loop Filter,” Adrian.
Maxim et al., IEEE Journal of Solid-State Circuits, vol. 36, No. 11, Nov. 2001.

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