Control signal generation circuit and semiconductor memory devic

Details Control signal generation circuit and semiconductor memory devic Control signal generation circuit and semiconductor memory devic

1997-01-10

1998-09-22

Zarabian, A.

Static information storage and retrieval

Addressing

Sync/clocking

365193, G11C 800

Patent

active

058124926

ABSTRACT:
A semiconductor memory device operates switched between a first readout mode in which data readout according to a specified activation of a column address strobe signal /CAS that shows a transition in synchronization with an external clock signal is output during a period including the specified activation of signal /CAS, and a second readout mode in which the readout data is output during a subsequent predetermined period of signal /CAS. A control circuit for controlling the data output timing from an output buffer activates the output buffer at an elapse of a predetermined time following the specified activation of signal /CAS in the first readout mode. In the second readout mode, the control circuit activates the output buffer according to activation of signal /CAS at a predetermined period.

REFERENCES:
patent: 5548560 (1996-08-01), Stephens et al.
patent: 5557582 (1996-09-01), Kawamoto
patent: 5629896 (1997-05-01), McClure

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