Control of voltages during erase and re-program operations...

Details Control of voltages during erase and re-program operations... Control of voltages during erase and re-program operations...

2007-10-30

2007-10-30

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185030, C365S185190, C365S185200

Reexamination Certificate

active

11334205

ABSTRACT:
A method for verifying an array cell of a memory device may include determining after each erase pulse or program pulse the threshold of a cell addressed through a selected array word-line and bit-line, by applying an identical voltage ramp to the selected array word-line and to the control gate of a reference cell, while biasing at a certain voltage deselected word-lines through distribution lines of the voltage generated by a charge pump generator. The method may further include temporarily decoupling the deselected word-lines from the distribution lines of the bias voltage for the duration of the voltage ramp.

REFERENCES:
patent: 7180787 (2007-02-01), Hosono et al.
patent: 1249841 (2002-10-01), None
patent: 1467377 (2004-10-01), None

Affiliated with

Also associated with

Rating

Control of voltages during erase and re-program operations... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Control of voltages during erase and re-program operations..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Control of voltages during erase and re-program operations... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3902225