Control of tristate buses during scan test

Details Control of tristate buses during scan test Control of tristate buses during scan test

2003-06-27

2004-11-23

Pert, Evan (Department: 2829)

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

C324S765010, C714S726000

Reexamination Certificate

active

06822439

ABSTRACT:

FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
[Not Applicable]
MICROFICHE/COPYRIGHT REFERENCE
[Not Applicable]
BACKGROUND OF THE INVENTION
Due to the increasing numbers of transistors that are incorporated on integrated circuits, exhaustive testing of integrated circuits is practically impossible. Rather, digital circuits are usually tested by applying a variety of test signals to the system and monitoring the output signals produced in response.
Adding to this technique, digital circuits have also been designed with memory stages which can be operated in one of two modes—a first mode where the memory stages operate primarily as designed, and a second mode where the memory stages are connected in series to form one or more extended shift registers, otherwise known as scan chains. During the second mode, bit patterns, known as test vectors, are shifted or scanned into the scan chains. The logic system is returned to its first mode configuration and permitted to operate for one clock. The logic system is then returned to the second mode and the results extracted from the logic system (again by scanning) are analyzed to determine the operability of the stages and interconnections of the logic system. This testing technique is usually referred to as “scan testing”.
Fault coverage measures the degree to which test vectors are capable of uncovering potential defects and faults. It is a goal of scan testing to achieve a high degree of fault coverage in a reasonable amount of time. Accordingly, there are a number of tools which generate a combination of test patterns which achieve a requisite degree of fault coverage in short amount of time.
Many of the digital circuits tested include tristate buses, which can be used by two or more entities. Competing requests for use by the two or more entities result in a resource contention. Use of test patterns which cause resource contention on tristate buses result in erroneous error reporting. Accordingly, automatic test pattern generators remove test patterns which cause resource contention on tristate buses and replace the test patterns with other test patterns which achieve the same fault coverage and avoid the resource contention. Nevertheless, some fault coverage is still lost.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art through comparison of such systems with embodiments presented in the remainder of the present application with reference to the drawings.
BRIEF SUMMARY OF THE INVENTION
Described herein are system(s), method(s), and apparatus for controlling tristate buses during scan testing. In one embodiment, there is presented a method for testing a circuit. The method for testing the circuit includes serially shifting a test pattern into at least a portion of the circuit. While serially shifting the test pattern, each of a plurality of tristate drivers except a default driver from the plurality of tristate drivers are disabled. The method also includes capturing a test response from at least a portion of the circuit. While capturing the test response from the portion of the circuit, each of the plurality of tristate drivers except a selected one of the plurality of drivers are disabled.
In another embodiment, there is described a system for testing a circuit. The system includes scan line registers, and a decoder. The scan line registers are for shifting a test pattern into at least a portion of the circuit and capturing a test response from at least a portion of the circuit. The decoder is for disabling each of a plurality of tristate drivers except a default driver from the plurality of tristate drivers while the scan line registers serially shift the test pattern, and disabling each of the plurality of tristate drivers except a selected one of the plurality of drivers while the scan line registers capture the test response.
In another embodiment, there is presented a circuit for testing a device under test. The circuit includes scan line registers and a decoder. The scan line registers shift a test pattern into at least a portion of the device under test and capturing a test response from at least a portion of the circuit. The decoder is connected to the scan line registers and disabling each of a plurality of tristate drivers except a default driver from the plurality of tristate drivers while the scan line registers serially shift the test pattern, and disables each of the plurality of tristate drivers except a selected one of the plurality of drivers while the scan line registers capture the test response.
These and other advantages and novel features of the present invention, as well as details of illustrated embodiments thereof, will be more fully understood from the following description and drawings.


REFERENCES:
patent: 5214655 (1993-05-01), Eichelberger et al.
patent: 5812561 (1998-09-01), Giles et al.
patent: 6487688 (2002-11-01), Nadeau-Dostie
patent: 6543018 (2003-04-01), Adusumilli et al.

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