Control of signal timing apparatus in automatic test systems usi

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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328 55, 328 63, 307269, 307590, 371 1, H03K 1700, G06K 504

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047898356

ABSTRACT:
A system which enables signals to be supplied at precisely desired times in an automatic test system. The apparatus includes a base delay memory which stores information related to a base time delay, while a vernier memory stores information relating to timing corrections to be made to the base time delay. The base delay memory controls a counter while the correction memory controls a vernier deskew apparatus for further delaying the output signal from the counter. To prevent carries from the vernier memory from influencing the base delay memory, the most significant bit of the vernier memory is of the same significance as the least significant bit of the base delay memory. The most significant bit of the vernier memory is also connected to drive the counter, in effect providing the counter with two least significant bits, and enabling a single base delay memory to control more than one signal timing paths.

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R. F. Herlein, "Optimizing the Timing Architecture of a Digital LSI Test System," I.E.E.E. International Test Conference (1983) Paper 8.5, pp. 200-209.
S. Sugamori et al., "Analysis and Definition of Overall Timing Accuracy in VLSI Test System," I.E.E.E. International Test Conference (1981) Paper 7.5, pp. 143-153.

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