Control of sense amplifier latch timing

Details Control of sense amplifier latch timing Control of sense amplifier latch timing

1991-01-28

1993-03-09

Popek, Joseph A.

Static information storage and retrieval

Addressing

Sync/clocking

365203, 36523003, G11C 800

Patent

active

051930765

ABSTRACT:
A static random access memory timing scheme is disclosed in which the latching of a sense amplifier is derived from substantially the same point in the a timing chain as is the precharge/equalization signal, which is derived from the row address transition detection signal (as is the word line gating signal). Fan-in is minimized so as to allow good immunity to gamma dot and parameter variations.

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