Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
1999-10-27
2001-08-28
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
Reexamination Certificate
active
06281731
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to input buffer circuits, and more particularly, to a differential receiver with a hysteresis characteristic adjusted and/or controlled, e.g., to be centered about a reference voltage.
BACKGROUND OF THE INVENTION
Several different integrated circuit technologies are available to circuit and system designers in which to realize their designs. These technologies include for example, bipolar, complementary metal oxide semiconductor (CMOS), bipolar-CMOS (Bi-CMOS), gallium arsenide (GaAs), and others. As would be expected, integrated circuits based on different technologies, or based on differing logic families within a technology, are often required to operate within a single system, and hence, must accurately communicate one with another.
One common problem that must be dealt with is the differing logic level voltages associated with the differing technologies, or between differing circuit families within a single technology. This problem is sometimes further exacerbated by supply voltage levels which may vary significantly, not only between different technologies, but even amongst circuits of like technologies. Additionally, it is now common to have a higher voltage to operate input/output circuits and a second lower voltage to operate internal circuits. In order to deal with such differences between circuits and technologies, designers rely upon input buffer circuits (also known as “voltage translators”, or “differential receivers”) that are capable of translating input signal levels from an external circuit into needed logic levels of internal circuits.
An input buffer circuit with a hysteresis characteristic has been used in order to prevent a situation where the input buffer circuit turns on or off by not only the input signal but also by noise associated with the input signal, thereby inhibiting the proper propagation of the input signal. The input buffer circuit with a hysteresis characteristic has two threshold values, namely V
Th
and V
Tl
. V
Th
is the threshold value for the case where the input signal rises, and V
Tl
is the threshold value for the case where the input signal falls. Accordingly, if the input signal becomes larger than V
Th
and the input buffer turns on, the circuit will not go low until the input voltage becomes smaller than V
Tl
. In this situation, noise with a width of V
Th
−V
Tl
is eliminated.
Ideally, the hysteresis characteristic is centered about a reference voltage of the input buffer circuit. However, power supply variations and component tolerances often result in a distorted hysteresis characteristic, e.g., non-symmetrical about the reference signal. Thus, there exists a need in the art for an input buffer circuit or differential receiver designed with a hysteresis characteristic that is capable of being held more closely centered about the reference signal.
DISCLOSURE OF THE INVENTION
Briefly summarized, in a first aspect the present invention comprises a metal oxide semiconductor (MOS) differential receiver which includes a hysteresis circuit for endowing the MOS differential receiver with a hysteresis characteristic, and means for adjusting the hysteresis characteristic about a reference voltage of the MOS differential receiver. The adjusting means includes means for establishing a dc backgate voltage differential between an input transistor and a reference transistor of the MOS differential receiver, wherein the reference transistor receives the reference voltage.
In another aspect, a metal oxide semiconductor (MOS) differential receiver is provided which includes a first transistor coupled for receiving a first signal and a second transistor coupled for receiving a second signal. A bias circuit is provided having a supply voltage coupled to the first transistor and the second transistor, as well as a current source. A hysteresis circuit is coupled in parallel with the second transistor between the supply voltage and the current source. When in operation, the first signal comprises an input signal, the second signal comprises a reference signal and an output signal is provided from an output of the first transistor. A bias voltage is applied as a dc backgate potential to at least one of the first transistor and the second transistor in order to adjust about the reference signal the hysteresis characteristic produced by the hysteresis circuit. In an enhanced embodiment, the backgate potential is adjusted to establish the hysteresis characteristic substantially symmetrical about the reference signal.
In still another aspect, a metal oxide semiconductor (MOS) differential receiver is provided which includes a first transistor coupled for receiving a first signal, and a second transistor coupled for receiving a second signal. A bias circuit provides a supply voltage to the first transistor and the second transistor, as well as a current source coupled to the first and second transistors. A hysteresis transistor is coupled in parallel with the second transistor, and a switching circuit is provided for gating the hysteresis transistor. The switching circuit is coupled between a reference signal plus a first offset voltage and the reference signal minus a second offset voltage for applying one of the reference signal plus the first offset voltage or the reference signal minus the second offset voltage to the gate of the hysteresis transistor. The switching circuit is controlled by a signal at an output of the first transistor. In operation, the first signal comprises an input signal, the second signal comprises the reference signal, and the signal at the output of the first transistor comprises an output signal of the differential receiver.
In a further aspect, a method is provided for adjusting a predetermined switching point of a differential receiver circuit which receives a logic signal input having first and second states. The differential receiver circuit includes an input transistor and a reference transistor, each coupled to a bias circuit. The method comprises: deriving a reference voltage for application to the reference circuit, the reference voltage having a voltage magnitude substantially equal to a voltage magnitude of the predetermined switching point; receiving the logic input signal at the input circuit; translating the logic input signal in the differential receiver circuit to an output having an output in a first state when the logic input signal is in a first state, and translating the output to a second state when the logic input signal is in a second state; modifying the switching point to a lower voltage level when the output changes to the first state, and modifying the switching point to a higher voltage level when the output changes to the second state, wherein the modifying includes disposing the lower level and the higher level about the predetermined switching point by establishing a backgate voltage differential between the reference transistor and the input transistor.
To restate, provided herein is an input buffer circuit comprising a differential receiver with a hysteresis characteristic that is advantageously controlled, e.g., to be centered about a reference signal. Tuning of the hysteresis characteristic is achieved by varying a backgate potential of at least one of the input transistor and the reference transistor of a MOS differential receiver implementation to thereby establish a dc backgate voltage differential between the input transistor and the reference transistor. A MOS differential receiver implemented in accordance with this invention provides improved sharpness at the switching thresholds and any degree of hysteresis. The switching thresholds are further constrained by a switching circuit connected to gate the hysteresis circuit by selectively applying the reference voltage to the hysteresis circuit plus a first predefined offset voltage, and minus a second predefined offset voltage. The differential receiver continues to operate with decreasing power supplies, and satisfactory operation, with common mode rejection, extends from sl
Fifield John A.
Houghton Russell J.
Pricer Wilbur D.
Tonti William R.
Heslin Rothenberg Farley & & Mesiti P.C.
International Business Machines - Corporation
Nu Ton My-Trang
Radigan, Esq. Kevin P.
Walsh, Esq. Robert A.
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