Control of a variable delay line using line entry point to...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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Details

C327S276000

Reexamination Certificate

active

07541851

ABSTRACT:
Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input signal (ClkIn) into the VDL. Specifically, VccVDL is regulated to be higher when the delay through the VDL is relatively small (when the entry point is toward the right (or minimum delay) edge of the VDL) and is reduced when the delay is relatively high (when the entry point is toward the left (or maximum delay) edge of the VDL). This provides for graduated delays across the stages of the VDL, but without the need to design each stage separately. Other benefits include a VDL/DLL design operable over a wider range of frequencies, and a reduced number of stages, including a reduced number of buffer stages. Moreover, when the disclosed technique is used, buffer stages may be dispensed with altogether. Additionally, the disclosed VDL architecture can be used in any situation where it might be advantageous to delay a signal through a variable delay as a function of VDL entry point.

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S. Kuge et al., “A 0.18-um 256-Mb DDR SDRAM with Low-Cost Post-Mold Tuning Method for DLL Replica, 11, Nov. 2000,” IEEE J. Solid State Circuits, vol. 35, No. 11, pp. 1680-1689.
U.S. Appl. No. 11/351,037, filed Feb. 8, 2006, Zimlich.
U.S. Appl. No. 11/132,502, filed May 19, 2005, Gomm et al.
S. Kuge et al., “A 0.18-μm 256-Mb DDR SDRAM with Low-Cost Post-Mold Tuning Method for DLL Replica,” IEEE J. Solid State Circuits, vol. 35, No. 11, pp. 1680-1689 (2000).

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