Control method of semiconductor memory device and...

Details Control method of semiconductor memory device and... Control method of semiconductor memory device and...

2006-07-25

2006-07-25

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233500

Reexamination Certificate

active

07082077

ABSTRACT:
A control method of a semiconductor memory device which enables control of an operation mode including an operation that might become a noise source by using an operation mode including an operation from which the influence of noise should be eliminated, and a semiconductor memory device are provided. First and second operation sections performing independent operations are provided, and a signal output section for outputting a second signal S2and a mode controller section for supplying a control signal C1are provided in the second operation section. The control signal C1is outputted from the mode controller section and the signal output section outputs the second signal S2to a memory cell array, thus performing a second operation. A predetermined first signal SS1is supplied to the signal output section from the first operation section, thus delaying an output response of a predetermined second signal. While the control signal C1is outputted from the mode controller section, the supply of the predetermined second signal to the memory cell array can be delayed. The influence of state transition in the second operation on the operation state of the first operation can be eliminated.

REFERENCES:
patent: 4875189 (1989-10-01), Obara
patent: 5555215 (1996-09-01), Nakagome et al.
patent: 6600688 (2003-07-01), Kawabata

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