Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Phase shift by less than period of input
Reexamination Certificate
1999-11-04
2001-12-11
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Phase shift by less than period of input
C327S144000, C327S233000, C327S176000
Reexamination Certificate
active
06329858
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a control method or a control system for signal transmission, which transmits a data signal on the basis of a reference clock between two circuits in such a device as a computer. Herein, it is to be noted that the control method or the control system is capable of easily and surely carrying out the signal transmission even in higher speeds data system.
Conventionally, methods and system for controlling signal transmission has such a problem that many receiving data which are transmitted especially over a long transmission line within a computer are incorrect. This is because, in a case where a long delay occurs to higher speed data with respect to a reference clock at a receiver side, a read timing by the reference clock can not accord with any data of data signals due to a long timing delay or big phase skew.
In order to remove the above-described problem, a clock skew adjustment system has been proposed in, for example, Japanese Unexamined Patent Publication No. Hei 2-197912, namely, 197912/1990.
Referring to
FIG. 1
, a reference clock A is supplied to and distributed in LSI-S (Large Scale Integration circuit of Sender side)
120
through a clock distribution gate
1
from a reference clock oscillator
10
in this system. Also, a reference clock B is supplied to and distributed in LSI-R (Large Scale Integration circuit of Receiver side)
130
through the clock distribution gate
1
from the reference clock oscillator
10
in the system.
Accordingly, data signals are transmitted from F/F (flip-flop circuit)
121
of LSI-S
120
on the basis of the reference clock A and received in F/F
131
of LSI-R
130
on the basis of the reference clock B. Generally, some skew occurs between phases of the reference clocks A and B respectively, because each transmission time is different in relation to the disposition between the clock distribution gate
1
and each of the LSI-S
120
and the LSI-R
130
.
However, the reference clocks A and B can be arranged so as to be in accordance with phases corresponding to the disposition between the LSI-S
120
and the LSI-R
130
and distributed to each of a clock distributor
122
of the LSI-S
120
and a clock distributor
133
of the LSI-R
130
.
Referring to a time chart illustrated in
FIG. 2
, in the case where phase skew does not occur between the reference clocks of LSI-S
120
and LSI-R
130
, sure data transmission can be executed, because, data is surely received one after another from the data signal by each leading edge of the same phased clock in F/F
121
,
131
, and
132
respectively.
The reference clocks A and B can be arranged without any phase skew inside of each LSI. However, the phase skew occurs in the LSI-R
130
against the LSI-S
120
by reason of the transmission time of the data signal corresponding to the disposition between the LSI-S
120
and the LSI-R
130
. Accordingly, the data signal sent from the F/F
121
may not surely be received by the clock timing in the LSI-R
130
. Especially in the higher speed data, a short difference between phases will become relatively long and, as a result, the correctness in the data reception is degraded.
For the purpose of removing of the above described weak point, as illustrated in
FIG. 1
, a delay detector
123
in the LSI-S
120
and a delay detector
134
in the LSI-R
130
are supplied respectively. The delay detectors
123
and
134
are connected with a transmission line for delay time verification to have the same course of the transmission line of the data signal. Accordingly, it is capable of detecting any phase skew by reason of the transmission delay of the data signal to be transmitted from the LSI-S
120
to the LSI-R
130
.
However, the conventional control method or control system described above requires much complicated control in order to surely transmit data signals at higher speeds in the case when the phase skew occurs by some delay timing on the data transmission line between the LSI-S and the LSI-R.
One of the reasons of the requirement for the complicated control is a necessity of clock distributors which accord to mutually phases of clocks distributed into the LSI-S and the LSI-R. Another reason is a necessity of a transmission line for delay time verification and a necessity of delay detectors which are connected to the transmission line. The transmission line is supplied between the LSI-S and the LSI-R, and the delay detectors detect phase skew by obtaining delay time of the data signal over the transmission line.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide a control method or a control system, which is used for signal transmission over a data transmission line between two circuits and simply executes the sure signal transmission even if any higher speed system of data.
According to an aspect of this invention, a control method is used for signal transmission wherein a data signal is transmitted between two circuits on the basis of a reference clock inside of a system. The sending side circuit transmits a sender side clock signal together with the data signal to a clock transmission line of the same course with a data transmission line for the data signal by using of a sender side reference clock. The receiving side circuit adjusts phases of the sender side clock signal and the data signal at input points of the transmission lines respectively, so as to be in accordance with a receiver side reference clock. And the receiving side circuit reads out data from an adjusted data signal by using of an adjusted clock by above adjusting.
One of the detailed adjusting includes the followings. The first one is to compare a phase of an adjusted clock by above adjusting with a phase of the receiver side reference clock. The second one is to obtain a phase difference between above clocks compared by above comparing. And the third one is to adjust phases of the sender side clock signal and the data signal from the sender side circuit respectively so as to accord with the receiver side reference clock, by using of an output clock having the above phase difference.
According to another aspect of this invention, a control system for signal transmission comprises at least one of first flip-flop circuits and a second flip-flop circuit on a sender side circuit. And the control system further comprises at least one of first phase adjusters and a third flip-flop circuit corresponding to the first flip-flop circuits, and a second phase adjuster and a phase comparison circuit at least corresponding to the second phase adjuster, on a receiver side circuit.
At least one of first flip-flop circuits is used for transmitting the data signal to a data transmission line and a second flip-flop circuit is used for transmit a sender side clock signal to a clock transmission line, by using of a sender side reference clock. At least one of first phase adjusters corresponding to the first flip-flop circuits is used for adjusting a phase of the data signal over the data transmission line and a second phase adjuster is used for adjusting a phase of the sender side clock signal over the clock transmission line.
One of the phase comparison circuit receives an adjusted clock by the second phase adjuster and a receiver side reference clock. And the phase comparison circuit compares their clocks and then feeds back a feedback clock having a phase difference obtained by above comparing, to the first and second phase adjusters, in order to make the phase difference zero by using of the feedback clock. The third flip-flop circuit is used for reading out data from the adjusted data signal from the first phase adjuster by using of the adjusted clock from the second phase adjuster.
REFERENCES:
patent: 4222009 (1980-09-01), Moulton et al.
patent: 4272690 (1981-06-01), Riney et al.
patent: 4823360 (1989-04-01), Tremblay et al.
patent: 5168182 (1992-12-01), Salerno et al.
patent: 5864250 (1999-01-01), Deng
patent: 5999023 (1999-12-01), Kim
patent: 6100737 (2000-08-01), Heiles
patent: 2-197912 (1990-08-01), None
Callahan Timothy P.
Luu An T.
McGuireWoods LLP
NEC Corporation
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