Control memory error correcting apparatus

Details Control memory error correcting apparatus Control memory error correcting apparatus

1991-09-30

1994-12-20

Beausoliel, Jr., Robert W.

Excavating

371 401, G06F 1134, H03H 1300

Patent

active

053752317

ABSTRACT:
A control memory error correcting apparatus includes a control memory, a microinstruction register, a control pattern generator, a control pattern storage register, and an operation inhibit signal generator. The control memory stores a microinstruction including a first field for controlling a first operation unit by a microinstruction pattern and a second field for generating a control pattern for controlling a second operation unit. The microinstruction register stores the microinstruction from the control memory. The control pattern generator generates the control pattern in accordance with the second field from the microinstruction register. The control pattern storage register stores the control pattern from the control pattern generator. The operation inhibit signal generator changes timings and destinations of the operation inhibit signals output to the first and second operation units and the control pattern storage register in accordance with the types of the error-detected fields when a correctable error is detected in any of the first and second fields stored in the microinstruction register.

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Fotland, D. A., "An Adaptable 1-MIPS Real-Time Computer", 1266 Hewlett Packard Journal, vol. 35, Feb. 1984, No. 2, Amstelveen, Nederland.

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