Control means for an integrated memory matrix display and its co

Details Control means for an integrated memory matrix display and its co Control means for an integrated memory matrix display and its co

1987-04-30

1989-04-25

Brigance, Gerald L.

Communications: electrical

Land vehicle alarms or indicators

Internal alarm or indicator responsive to a condition of the...

340784, G09G 320

Patent

active

048252026

DESCRIPTION:

BRIEF SUMMARY
The present invention relates to a control means for an integrated memory matrix display and to its control process.
The invention more particularly applies to any matrix display with an active matrix having an electrooptical display material, whereof an optical property such as opacity, refractive index, transparency, absorption, etc. can be modified with the aid of a random excitation.
The invention particularly advantageously applies to liquid crystal matrix displays without grey level, e.g. used as converters of electrical informations into optical informations for the real time processing of optical images for analog display purposes.
For reasons of clarity, throughout the remainder of the text the example of the liquid crystal will be used, although any other electrooptical material can be considered.
FIG. 1a diagrammatically shows a matrix display with an active matrix of a known type and FIG. 1b shows the control circuit associated with an elementary image point of said display.
FIG. 1a shows first and second insulating walls 1, 3 facing one another and which are kept spaced and sealed by a joint 2 arranged on the periphery thereof. Between said walls 1, 3 is inserted a display material 4 having an optical property.
Over the inner face of one of the walls 1 are distributed n parallel row conductors L.sub.i and m parallel column conductors C.sub.j, which intersect with the row conductors, i and j being integers such that 1.ltoreq.i.ltoreq.n and 1.ltoreq.j.ltoreq.m, the row conductors and column conductors carrying electrical signals appropriate for the excitation of material 4.
At the intersection 11 of each row conductor L.sub.i with each column conductor C.sub.j, there is a switch 5, such as a field effect transistor connected to an electrode E.sub.ij and to conductors L.sub.i and C.sub.j. Moreover, the inner face of the other wall 3 is covered with a conductive material serving as a counterelectrode 10, which is raised to a reference potential.
An image point I.sub.ij is defined in said display by the overlap region of an electrode E.sub.ij land the counterelectrode 10, electrode E.sub.ij and counterelectrode 10 respectively forming the two armatures or coatings of a capacitor, whose display material, in particular the liquid crystal placed between these armatures forms the dielectric.
In the particular case where the display material is a liquid crystal film, in order to prevent deterioration thereof, the counterelectrode 10 is raised to a reference potential V.sub.R, whose value is periodically inverted and the column and row conductors carry electrical signals e.g. in square-wave form.
FIG. 1b shows in known manner the electric circuit diagram of a control circuit associated with an image point I.sub.ij, the latter being represented by a capacitor. Thus, with the intersection of a row conductor L.sub.i and a column conductor C.sub.j is associated a field effect transistor 5 connected to one of the armatures of the capacitor corresponding to electrode E.sub.ij. The other armature of said capacitor corresponding to the counterelectrode is raised to the reference potential V.sub.R. This capacitor makes it possible to store the information to be displayed at image point I.sub.ij.
When applying an electrical signal to row L.sub.i such that the potential applied to the corresponding transistor 5 is equal to or higher than the threshold voltage of said transistor, the latter is in the on state. It then makes it possible to transmit the electrical signal applied to column C.sub.j to electrode E.sub.ij to which it is connected. When the electrical signal applied to row L.sub.i is such that the resulting potential applied to the corresponding transistor 5 is below the threshold voltage of transistor 5, the latter passes into the off state no matter what the signal of column C.sub.j and transmits no signal to electrode E.sub.ij, which will therefore retain its initial charge. This applies to each elementary image point of the display.
The column electrical signal transmitted to electrode E.sub.ij produce

REFERENCES:
patent: 4141000 (1979-02-01), Thomas et al.
patent: 4236155 (1980-11-01), Nagata
patent: 4365242 (1982-12-01), Yasuda et al.
patent: 4646074 (1987-02-01), Hashimoto
patent: 4701799 (1987-10-01), Yoshimura
patent: 4716403 (1987-12-01), Morozumi

Affiliated with

Also associated with

Rating

Control means for an integrated memory matrix display and its co does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Control means for an integrated memory matrix display and its co, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Control means for an integrated memory matrix display and its co will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1198542