Control loops for low power, high speed PRML sampling data detec

Details Control loops for low power, high speed PRML sampling data detec Control loops for low power, high speed PRML sampling data detec

1997-08-29

1999-03-23

Psitos, Aristotelis M.

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Data clocking

364179, 364602, G11B 0509

Patent

active

058868429

ABSTRACT:
A power-reduced digital control within a feedback control loop of a sampling data detection channel controls a predetermined operating parameter of the channel in which an analog to digital converter provides digital samples of information in the channel at a predetermined channel clock rate. The digital control comprises a parameter error extraction circuit clocked at the predetermined channel rate which is connected to receive digital samples from the analog to digital converter, and which extracts parameter error values from the digital samples; an averaging circuit for averaging the extracted parameter error values over an integral submultiple of the predetermined channel clock rate; and a parameter error processing circuit which is connected to the parameter error extraction circuit and clocked at the integral submultiple of the predetermined channel rate for generating and putting out digital control values within the feedback control loop for controlling the predetermined operating parameter. The parameter may be timing, gain or DC offset, and the sampling data detection channel may be a PRML channel of a magnetic hard disk drive. A power-reduced control method is also described.

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Cideciyan, Dolivo, Hermann, Hirt, Schott, "A PRML System for Digital Magnetic Recording" IEEE Jour. Sel. Areas in Comm., vol. 10, No. 1, Jan. 1992, pp. 38-56.

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