Control logic implementation for a non-blocking switch network

Details Control logic implementation for a non-blocking switch network Control logic implementation for a non-blocking switch network

2007-03-27

2007-03-27

Cardone, Jason (Department: 2145)

Electrical computers and digital processing systems: multicomput

Multicomputer data transferring via shared memory

C709S214000, C711S200000

Reexamination Certificate

active

10093920

ABSTRACT:
The present invention relates to switching technology in computer networks and in particular to a method and system for switching information packets through a m input, n output device. According to the invention it is proposed to temporarily buffer said packets according to a new, self-explanatory, preferred a linear addressing scheme in which a respective buffer location of consecutive stream packets results from a respective self-explanatory, or linear, respectively, incrementation of a buffer pointer. Preferably, a matrix of FIFO storage elements (10,11,12,13) having an input and an output crossbar can be used for implementing input/output paralleling modes (ILP,OLP) and multiple lanes and achieving address input/output scaling up to a single cycle.

REFERENCES:
patent: 5924111 (1999-07-01), Huang et al.
patent: 6366289 (2002-04-01), Johns
patent: 6657998 (2003-12-01), Li
patent: 2003/0046429 (2003-03-01), Sonksen

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