Control logic for a sequential data buffer using byte read-enabl

Details Control logic for a sequential data buffer using byte read-enabl Control logic for a sequential data buffer using byte read-enabl

1992-04-03

1996-11-05

Lee, Thomas C.

Boots, shoes, and leggings

39542109, 364DIG1, 3642387, 3642445, 3642624, 3642631, 364DIG2, 3649476, 364948, 377 81, G06F 900, G06F 930

Patent

active

055726828

ABSTRACT:
Shift-based control logic is used, in an exemplary embodiment, to implement in a microprocessor a circular prefetch queue that stores variable length instructions and transfers four instruction bytes at a time to an instruction decoder. The prefetch queue (10) includes a 16 byte sequential prefetch buffer (12). Access to the buffer is controlled by the shift-based control logic (14) which includes shifter logic that defines a four byte transfer window corresponding to an index byte together with the next three bytes in sequence. For each four-byte transfer operation, the shifter logic enables the four bytes within the transfer window to be read out for transfer to the instruction decoder (20). A transfer operation is initiated by the decoder, which presents the shift-based control logic with a bytes-used indicator, or shift increment. The shift increment denotes the number of bytes used by the previous four byte transfer via a four bit, one-hot selection. In response to receiving the shift increment, the control logic shifts the transfer window an amount specified by the shift increment in preparation for the next four byte transfer.

REFERENCES:
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patent: 4720779 (1988-01-01), Reynard et al.
patent: 4953121 (1990-08-01), Muller
patent: 5050067 (1991-09-01), McLagan et al.
patent: 5113515 (1992-05-01), Fite et al.
patent: 5317701 (1994-05-01), Reininger et al.
Murray et al. "Micro-Architecture of the VAX 9000", IEEE 1990 pp. 44-53.

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