Control gate driver circuit for a non-volatile memory and memory

Details Control gate driver circuit for a non-volatile memory and memory Control gate driver circuit for a non-volatile memory and memory

1996-08-23

1998-02-24

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518526, 36518529, 36518533, 365218, G11C 1134, G11C 700

Patent

active

057217041

ABSTRACT:
A control gate driver circuit (900) provides a variety of voltages to a control gate (21) of a floating gate nonvolatile memory cell (10) using a single circuit. During a read mode, a bias circuit (920) and a reference transistor (925) bias a pass transistor (936) connected to the output of a level shifter (910) to be slightly conductive and thus biases control gates without the need for a charge pump. During programming, a pulse circuit (940) gradually builds the program voltage provided to cells along a selected row, allowing the use of smaller pass transistors (932, 934) and smaller capacitors in the charge pump of the supply (930). Cells in an unselected row are driven to a different voltage, decreasing junction leakage and maintaining high disturb voltage in cells in the unselected row. The control gate driver circuit (900) is implemented using only P-channel pass transistors, eliminating the need for a costly triple-well process.

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patent: 5579262 (1996-11-01), Song
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Ser. No.: 08/603,939; Filing Date: Feb. 20, 1996; Inventor: Kuo-Tung Chang et al. "Method for Operating a Memory Array.".

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