Control circuit using delay lines to generate clock and control

Details Control circuit using delay lines to generate clock and control Control circuit using delay lines to generate clock and control

1996-03-04

1996-12-24

Miska, Vit W.

Horology: time measuring systems or devices

Time interval

Electrical or electromechanical

368120, 364270, 395557, G04F 800, G06F 104

Patent

active

055879721

ABSTRACT:
A control signal generator for generating a plurality of control and timing ignals which are supplied to a scan converter. The control and timing signals are utilized by the logic elements of the scan converter to process the incoming pixel data from a missile's seeker allowing the data to be supplied to a video monitor for viewing. The control signal generator includes a state machine which generates four state variable signals and a cycle counter which generates a binary count thirty one signal which allows the state machine to cycle through six predetermined states until the scan converter completes processing of incoming pixel data from each detector of the missile's seeker. The count thirty one signal and the four state variable signals are decoded by five decoders which generate the timing and control signals for the logic elements of the scan converter. Some of the timing and control signals are delayed by five and fifteen nanosecond delay lines prior to being supplied to the logic elements of the scan converter.

REFERENCES:
patent: 4688212 (1987-08-01), MacGinitie
patent: 4882683 (1989-11-01), Rupp et al.
patent: 5212723 (1993-05-01), Griesshaber
patent: 5390304 (1995-02-01), Leach et al.

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