Control circuit of dynamic random access memory

Details Control circuit of dynamic random access memory Control circuit of dynamic random access memory

1991-06-17

1994-06-14

Heyman, John S.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36523003, 365233, 371 22, G11C 700

Patent

active

053216660

ABSTRACT:
A control circuit of a memory system including a dynamic random access memory may include a first integrated circuit formed on a common substrate. The first integrated circuit may include a circuit responsive to an external memory access request signal for generating a control signal for controlling an operation timing of the dynamic random access memory to supply the control signal to the dynamic random access memory and a circuit for generating an address signal for specifying an address of the dynamic random access memory to be accessed to supply the address signal to the dynamic random access memory. A second integrated circuit includes a read/write circuit for reading data from the dynamic random access memory and for writing data in the dynamic random access memory.

REFERENCES:
patent: 4984210 (1991-01-01), Kumanoya et al.
patent: 5036493 (1991-06-01), Nielsen
patent: 5036494 (1991-07-01), Wise et al.
patent: 5058074 (1991-10-01), Sakamoto
patent: 5159572 (1992-10-01), Morton
patent: 5175707 (1992-12-01), Murotani

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