Control circuit having clock control unit

Details Control circuit having clock control unit Control circuit having clock control unit

2000-06-01

2002-01-29

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

Having selection between plural continuous waveforms

C327S544000, C326S093000

Reexamination Certificate

active

06342795

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a control circuit having a functional block which is formed on a semiconductor substrate, performs a predetermined operation in response to an input signal instructing an operative status under the control of a clock signal, stops the operation in response to an input signal instructing an inoperative status, and has therein a clock control unit for controlling the supply of the clock signal to the functional block or not.
2. Description of the Related Art
Hitherto, in a semiconductor integrated circuit obtained by integrating a plurality of functional blocks on a semiconductor substrate, a control circuit
1
shown in
FIG. 16
is adopted for performing a control synchronously with a clock signal supplied from an external clock.
The control circuit
1
has a plurality of functional blocks
3
on a semiconductor substrate
2
in a manner similar to a conventionally used semiconductor integrated circuit. Each of the functional blocks
3
comprises a ROM, a RAM, an I/F circuit, and a random logic circuit having a predetermined function. Each of the functional blocks
3
is connected to a common data bus
4
and is accessed by an external CPU via the data bus
4
. As shown in
FIG. 17
, the functional block
3
further comprises a combinatorial logic circuit
5
, a flip flop
6
and a control register
7
as a clock control unit. An input signal is supplied to the combinatorial logic circuit
5
via a signal line of the common data bus
4
.
Further, a clock signal is supplied through a signal line
4
a
included in the common data bus
4
to the control register
7
. An instruction signal for instructing whether the clock signal is supplied or not is sent to the control register
7
via a signal line
4
b included in the common data bus
4
. When the instruction signal instructs the supply of a clock signal, the clock signal is supplied to a clock terminal of the flip flop
6
via a signal line in the functional block
3
.
In an operative status in which an input signal is supplied to the functional block
3
and the functional block
3
performs a predetermined operation, “1” is latched in the control register
7
. At this time, the control register
7
outputs a clock signal to a signal line
4
c.
On the other hand, in an inoperative status in which no input signal is supplied to the functional block
3
and the functional block
3
does not perform a predetermined operation, a signal of “0” is latched in the control register
7
. In this case, the control register
7
does not output a clock signal to the signal line
4
c.
In the operative status, in response to the input signal supplied via the signal line
4
c
to the combinatorial logic circuit
5
, a predetermined process is performed under the control of the clock signal. The result of the process is outputted as an output signal to the outside of the functional block
3
.
Since the supply of the clock signal can be stopped in the inoperative status in which no input signal is supplied to the functional block
3
and the functional block
3
does not perform the predetermined operation, power consumed by the clock signal can be suppressed.
In the conventional control circuit, however, since the supply of the clock signal is controlled by the input signal supplied from the outside to the functional block
3
, it is necessary to provide a function of determining the timing to stop the functional block
3
on the outside of the functional block
3
or design the circuit so that the control unit for generating the clock control signal operates synchronously with the input signal.
It therefore causes a problem such that the control is complicated and the size of the circuit is increased.
SUMMARY OF THE INVENTION
The present invention has been achieved in consideration of the above problems. It is an object of the invention to provide a control circuit of a simplified circuit construction and control while power consumed by the continuous supply of a clock signal to a functional block which is in an inoperative status is reduced.
It is another object of the invention to provide a control circuit comprising: a functional block which is provided on a semiconductor substrate, performs a predetermined operation in response to an input signal requesting an operative status under the control of a clock signal, and stops the predetermined operation in response to a signal requesting an inoperative status; and a clock control unit which is provided in the functional block and controls the supply of the clock signal to the functional block, wherein the functional block supplies a status detection signal indicative of the operative status or the inoperative status to the clock control unit, when the status detection signal supplied from the functional block indicates the operative status, the clock control unit supplies the clock signal to operate the functional block, and when the status detection signal supplied from the functional block indicates the inoperative status, the clock control unit stops the supply of the clock signal to stop the functional block. Consequently, the operation of the functional block which is not in use can be stopped and it is unnecessary to provide a particular control unit for supplying a control signal to control the clock signal on the outside of the functional block.
It is further another object of the invention to provide a control circuit, wherein a plurality of the functional blocks are connected to each other, some of the plurality of functional blocks have different operation timings, at least one functional block which operates first is set to be in the inoperative status when an output signal is outputted to at least one functional block which operates later, and a status detection signal indicative of the inoperative status is outputted to a clock control unit of the functional block which operates first. Consequently, even when the functional block which operates first and the functional block which operates later are not simultaneously in the operative status, data can be supplied to the functional block which operates later. The maximum power consumption of the clock signal by the simultaneous operation can be therefore reduced. Further, due to the supply of a new input signal to the functional block which operates first, an output signal outputted, before the supply, to the functional block which operates later does not change. Consequently, the functional block which operates later can be prevented from an erroneous operation and, further, the circuit designing can be facilitated.
Further another object of the invention is to provide a control circuit wherein the clock control unit further comprises a frequency dividing circuit. The occurrence of a hazard in the waveform of a clock signal and a fluctuation in the pulse width due to an error in time between a clock signal supplied from the outside to the clock control unit and a clock signal supplied from the clock control unit to a functional block can be prevented. Thus, the functional block can be prevented from an erroneous operation.
Further another object of the invention is to provide a control circuit wherein the functional block has a plurality of operative statuses, and the clock control unit supplies a clock signal of a dividing ratio which varies according to the operation status of the functional block. Also in the functional block having the plurality of operative statuses, the occurrence of a hazard in the waveform of a clock signal and a fluctuation in the pulse width due to an error in time between a clock signal supplied from the outside to the clock control unit and a clock signal supplied from the clock control unit to a functional block can be prevented. Thus, the functional block can be prevented from an erroneous operation.


REFERENCES:
patent: 5585745 (1996-12-01), Simmons et al.
patent: 5675282 (1997-10-01), Saito
patent: 5768213 (1998-06-01), Jung et al.
patent: 6100732 (2000-08-01), Penry et al.
patent: 6-83756 (1994-06-01),

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