Control circuit for terminating a memory access cycle in a memor

Details Control circuit for terminating a memory access cycle in a memor Control circuit for terminating a memory access cycle in a memor

1998-10-30

2000-03-07

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

3652335, 365191, 365194, G11C 800

Patent

active

060349174

ABSTRACT:
A control circuit for terminating a memory access cycle in a memory block having at least one memory cell is disclosed. The at least one memory cell has unique process characteristics. The control circuit includes a memory block activation circuit for generating a memory block activation signal. The memory block activation circuit includes a reset circuit for terminating the memory block activation signal when activated. The control circuit also includes a memory access cycle tracking circuit, responsive to the memory block activation signal, for generating a reset signal. The memory access cycle tracking circuit includes the unique process characteristics of the at least one memory cell for tracking an operation of the at least one memory cell. The reset signal activates the reset circuit so as to terminate the memory block activation signal and terminate the memory access cycle in the memory block.

REFERENCES:
patent: 5586286 (1996-12-01), Santeler et al.
patent: 5596539 (1997-01-01), Passow et al.
patent: 5724294 (1998-03-01), Khieu

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