Control circuit for semiconductor memory device

Details Control circuit for semiconductor memory device Control circuit for semiconductor memory device

1999-05-10

2001-01-30

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S203000, C365S210130, C365S230060

Reexamination Certificate

active

06181640

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a control circuit for semiconductor memory device, more particularly to a control circuit capable of reducing power consumption by controlling WRITE operation of SRAM (Static Random Access Memory).
Generally, SRAM memory cell includes a flip-flop circuit for data storage and two switch elements (e.g. two access transistors). In SRAM, if the access transistors are applied with a pulse through a word line so that the cell transistor is turned on, access for data writing or reading to/from the memory cell can be made. In addition, if the write signal is active (e.g. “high” level), data transfer can be made between a pair of bit lines and a pair of data bus lines.
In addition, the data of SRAM is statically maintained to a cell without any refresh operation due to the feedback effect of the flip-flop included therein, as long as the power is supplied thereto. This is contrary to that of DRAM.
FIG.1
is a circuit diagram illustrating a conventional SRAM of a semiconductor memory device, which includes a dummy bit line unit.
Referring to
FIG. 1
, the reference character
60
represents the dummy bit line unit and the reference character
80
represents a memory circuit unit (e.g. SRAM circuit unit) including memory cell array. The SRAM circuit unit
80
includes NMOS transistors NM
1
and NM
2
for bit line precharging, NMOS transistors NM
3
and NM
4
for bit line static precharging, a plurality of memory cells
10
, NMOS transistors NM
5
and NM
6
for column selecting, and a sense amplifier
20
. Each of the NMOS transistors NM
1
and NM
2
has a gate applied with a precharge signal PRE. Thus, the NMOS transistors NM
1
and NM
2
are turned on by the high level of the precharge signal PRE, which in turn, precharge the bit line BL and the inverted bit line /BL, respectively. The static precharge NMOS transistor NM
3
is diode-coupled from the power signal VDD to the bit line BL and the static precharge NMOS transistor NM
4
is diode-coupled from the power signal VDD to the inverted bit line /BL. The memory cell
10
is coupled between the bit line BL and the inverted bit line /BL. Each of the NMOS transistors NM
5
and NM
6
has a gate applied with a column signal COL for selecting the bit line and the inverted bit line /BL, respectively. The sense amplifier
20
is coupled between a data bus line DBL and an inverted data bus line /DBL and is activated by a sense enable signal SE to sense and amplify the data.
The dummy bit line unit
60
of
FIG. 1
produce an inverted dummy bit line signal /S
1
in response to the precharge signal PRE from an address signal transition detector (see
FIG. 2
) and a plurality of word line signals WL [M-1:0] from a word line signal generator (not shown). The dummy bit line unit
60
comprises an NMOS transistor NM
62
whose drain-source path is coupled between the power voltage VDD and the dummy bit line DUBL and whose gate is applied with the precharge signal PRE; a plurality of NMOS transistors NM
64
, NM
66
and NM
68
each drain-source path being coupled between the dummy bit line DUBL and the ground and each gate being applied with the corresponding word line signal WL[M-1:0], respectively; and an inverter IV
62
whose input is coupled to the dummy bit line DUBL for producing the inverted dummy bit line signal /S
1
.
In addition, the memory cell array of conventional SRAM further includes NMOS transistors NM
7
and NM
8
for write operation, two CMOS inverters
30
and
40
. Each of the NMOS transistors NM
7
and NM
8
has a gate applied with an internal write signal WR and is activated the high level of the write signal WR, that is the duration for write operation. The CMOS inverter
30
includes a PMOS transistor PM
1
and an NMOS transistor NM
9
coupled, in series, between the power voltage VDD and ground VSS. Also, the output of the CMOS inverter
30
is coupled to the drain of NMOS transistor NM
8
and the input thereof is coupled for receiving a data input signal DIN. The CMOS inverter
40
includes a PMOS transistor PM
2
and an NMOS transistor NM
10
coupled in series, between the power voltage VDD and ground VSS. Also, the input of the CMOS inverter
40
is coupled to the output of the CMOS inverter
30
and the output thereof is coupled to the drain of the NMOS transistor NM
7
.
In the meantime, the bit line BL is coupled between the NMOS transistor NM
1
for bit line precharge and the NMOS transistor NM
5
for selecting a column, while the inverted bit line /BL is coupled between the NMOS transistor NM
2
for precharging and the NMOS transistor NM
6
for selecting. The data bus line DBL is coupled between the NMOS transistor NM
5
for selecting and the NMOS transistor NM
7
for writing, while the inverted data bus line /DBL is coupled between the NMOS transistor NM
6
for selecting and the NMOS transistor NM
8
for writing.
The memory cell
10
includes two PMOS transistors PM
3
and PM
4
, and four NMOS transistors NM
11
, NM
12
, NM
13
and NM
14
. The memory cell
10
further includes two storage nodes N
1
and N
2
. The PMOS transistor PM
3
, the storage node N
1
and the NMOS transistor NM
11
, are coupled in series, between the power voltage VDD and the ground VSS. Likewise, the PMOS transistor PM
4
, the storage node N
2
and the NMOS transistor NM
12
, are coupled in series, between the power voltage VDD and the ground VSS. For the NMOS access transistor NM
13
, the gate thereof is coupled to the corresponding word line WL and the source-drain path thereof is coupled between the storage node N
1
and the bit line BL. Also, for the NMOS access transistor NM
14
, it's gate is coupled to the word line WL and it's source-drain path is coupled between the storage node N
2
and the inverted bit line /BL.
In addition, in the memory cell
10
, the gates of the PMOS transistor PM
3
and the NMOS transistor NM
11
are coupled to the storage node N
2
, while the gates of the PMOS transistor PM
4
and the NMOS transistor NM
12
are coupled to the storage node N
1
.
The operation of conventional SRAM of semiconductor memory device having the structure as described above will be explained.
If the high level of the precharge signal PRE is applied to the gates of the precharge NMOS transistors NM
1
and NM
2
, the NMOS transistors NM
1
and NM
2
should turned on so as to precharge the bit line BL and the inverted bit line /BL, respectively.
If the precharge signal PRE is “high” state, the NMOS transistor NM
62
of the dummy bit line unit
60
is turned on so that the dummy bit line DUBL is precharged to “high” level and the inverted dummy bit line signal /S
1
, which is the output of the inverter IV
62
, becomes “low” level. In this condition, if any one of M word lines WL[M-1:0] is activated on “high” level, the corresponding NMOS transistor NM
64
, NM
66
or NM
68
is turned on so that the dummy bit line DUBL becomes “low” level and the inverted dummy bit line signal /S
1
(that is the output of the inverter IV
62
) becomes “high” level.
In the read operation of the data stored in the memory cell
10
, the sense amplifier
20
is activated by the high level of sense enable signal SE, so as to sense and amplify the difference in voltages between the storage node N
1
and the storage node N
2
, through the bit line BL and the inverted bit line /BL, and then produce its result through the output node DOUT.
In the write operation of the data to the storage nodes N
1
and N
2
of the memory cell
10
, the NMOS transistor NM
7
is turned on by the high level of the internal write signal WR applied to the gate thereof, so that the data bus line DBL is electrically coupled to the output of the CMOS inverter
40
. In addition, the NMOS transistor NM
5
is turned on by the high level of the column signal COL so that the data bus line DBL and the bit line BL is electrically coupled to each other. The access transistors NM
13
and NM
14
are also turned by the high level of word line signal. Accordingly, the output data of the CMOS inverter
40
i

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