Control circuit for selecting the greater of two voltage...

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

Reexamination Certificate

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Details

C327S534000, C327S537000

Reexamination Certificate

active

06774704

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to integrated circuits, and in particular to the comparison and selection of the greater of two voltage signals in an integrated circuit.
BACKGROUND OF THE INVENTION
FIG. 1
is a simplified block diagram showing a non-volatile memory (NVM) device
100
, which represents one type of integrated circuit that utilizes multiple voltage sources. NVM device
100
includes an array
110
of NVM cells
115
, and peripheral control circuitry located around array
110
including an input/output (I/O) control circuit
120
, a word line control circuit
130
, an optional address decoder
135
, a bit line control circuit
140
, a bit line (Y) decoder
145
, and a sense amplifier circuit
150
. NVM cells
115
are arranged in rows and columns such that each row of NVM cells
115
is connected to an associated word line WL
0
through WL
8
, and each column of NVM cells
115
is connected to two associated bit lines BL
0
through BL
8
.
Operation of NVM device
100
will now be described in detail with reference to FIG.
1
. Data, address (ADDR), and control (R/W/E) signals are transmitted through I/O control circuit
120
during read, write, and erase operations. During write operations, address data and an associated data word are respectively transmitted via I/O control circuit
120
to word line control circuit
130
(via optional address decoder
135
) and to bit line control circuit
140
. Word line control circuit
130
uses the address data to pass an appropriate programming voltage onto an associated word line (e.g., word line WL
0
), and bit line control circuit
140
then drives selected bit lines using an appropriate programming voltage to program selected NVM cells
115
of the selected row. According to one convention, the NVM cells
115
that are programmed store a logic “1” data value, and those NVM cells that remain unprogrammed store a logic “0” data value. During subsequent read operations, address data associated with selected data word is transmitted via I/O control circuit
120
to write line driver circuit
130
, which uses the address data to apply an appropriate read voltage on the associated word line (e.g., word line WL
0
), thereby causing the selected data word to be read from the NMV cells onto bit line BL
0
through BL
7
. The thus-read data word is then transmitted via Y-decoder
145
to sense amplifier circuit
150
, which in turn passes the selected data word to I/O control circuit
120
for transmission out of NVM device
100
. Finally, during erase operations, the word lines and bit lines are maintained at an appropriate voltage level that causes all programmed NVM cells
115
to be erased. Those of ordinary skill in the art will recognize that the above explanation is greatly simplified, and that many variations in the described operations are possible.
Referring to the upper left corner of
FIG. 1
, in addition to the peripheral control circuitry described above, NVM device
100
includes voltage sources
160
and
170
that respectively generate a first (read) voltage signal V
1
and second (program) voltage signal V
2
, which are transmitted to word line control circuit
130
and bit line control circuit
140
. Voltage signals V
1
and V
2
are selectively passed by these control circuits to the bit lines and word lines in order to facilitate the read and program/erase operations mentioned above.
FIG. 2
is a simplified circuit diagram showing a portion of word line control circuit
130
in additional detail. Word line control circuit
130
includes a conventional voltage control circuit
132
and a word line driver
136
that are used in combination to couple an associated word line WL to first voltage signal V
1
, second voltage signal V
2
, or ground (i.e., zero Volts). Voltage control circuit
132
includes a first PMOS transistor
133
connected between the first voltage source (i.e., voltage source
160
, see
FIG. 1
) and an output node
134
, and a second PMOS transistor
135
connected between the second voltage source (i.e., voltage source
170
, see
FIG. 1
) and output node
134
. Note that PMOS transistor
133
is controlled by second voltage signal V
2
, and PMOS transistor
135
is controlled by first voltage signal V
1
. Word line driver
136
includes a PMOS transistor
137
and an NMOS transistor
138
that are connected in series between output node
134
of voltage control circuit
132
and ground. PMOS transistor
137
and NMOS transistor
138
are controlled by a word line control signal VIN. During operation, voltage control circuit
132
passes a maximum voltage V
MAX
, which is the greater (i.e., most positive voltage) of first voltage signal V
1
and second voltage signal V
2
, to driver
136
, which in turn applies either V
MAX
or ground onto word line WL in accordance with word line control signal V
IN
.
A problem with conventional voltage control circuit
132
arises when voltage signals V
1
and V
2
are within one threshold voltage of each other. In particular, referring to
FIG. 2
, when voltage signals V
1
and V
2
vary by less than one threshold voltage of PMOS transistors
133
and
135
, then both of these transistors remain turned off and output node
134
remains floating, thereby potentially causing a latch up condition, and possibly causing damage to NVM device
100
by coupling voltage sources
160
and
170
together. This problem arises, for example, when voltage signals V
1
and V
2
are asynchronously changed between relatively low voltages used to perform read operations, and relatively high voltages utilized during program/erase operations. That is, when voltage supply
160
changes voltage signal V
1
between a read voltage level and a program voltage level, depending upon the current operation, and voltage supply
170
similarly changes voltage signal V
2
between a read voltage level and a program voltage level, and voltage supplies
160
and
170
operate asynchronously, then several situations can arise in which these voltage signals are within one threshold voltage of each other, as set forth in the following example.
FIG. 3
is a timing diagram showing exemplary voltage signals V
1
and V
2
that produce the problem mentioned above. In particular,
FIG. 3
shows voltage signals V
1
and V
2
during a read (normal) operation (e.g., time T0 through T2) and a subsequent program operation. During read operations, voltage signal V
1
is selectively adjustable (trimmable) by a user/manufacturer to be within a voltage range between a maximum value V
READ

MAX
(e.g., system voltage VDD plus one Volt) and a minimum value V
READ

MIN
(e.g., system voltage VDD minus one Volt). At the same time, voltage V
2
is maintained at system voltage VDD. That is, depending on how V
1
is trimmed, during read operations voltage signal V
1
may be higher or lower than voltage signal V
2
. Conversely, during program operations (e.g., time T2 through T5), voltage signal V
1
is raised to a program verify voltage V
VERIFY
(e.g., VDD plus two or more Volts), and voltage V
2
is raised to a program voltage V
PROGRAM
(e.g., 10 Volts). Of course, during a subsequent read operation, voltage signals V
1
and V
2
return to their previous read levels, as indicated after time T5. As described above, voltage signals V
1
and V
2
are selectively utilized by bit line control circuit
140
to control the bit lines BL
0
-BL
8
of NVM device
100
, and are transmitted to conventional voltage control circuit
132
of word line control circuit
130
(see FIG.
2
).
In the example indicated by the timing diagram in
FIG. 3
, there are several situations in which first voltage signal V
1
and second voltage signal V
2
“cross over” (i.e., signal V
1
changes from being lower than signal V
2
to being higher than signal V
2
, or vice versa) or are otherwise within one threshold voltage of each other, which can cause PMOS transistors
133
and
135
of conventional voltage control circuit
132
(see
FIG. 2
) to erroneously turn off. First, voltage signal V
1
may be erroneously trimmed to a

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