Control circuit for resetting a snoop valid bit in a dual port c

Details Control circuit for resetting a snoop valid bit in a dual port c Control circuit for resetting a snoop valid bit in a dual port c

1991-05-01

1994-06-07

Gossage, Glenn

Static information storage and retrieval

Magnetic bubbles

Guide structure

36523005, 364DIG2, G06F 1200

Patent

active

053197682

ABSTRACT:
A control circuit for a dual port cache tag memory is used to reset a snoop valid bit for an entry addressed through one of the dual ports. This port snoops a main memory bus, and a cache tag hit which occurs during a write operation to the main memory bus indicates that the snoop valid bit for the addressed entry should be reset. In order to avoid errors in resetting the snoop valid bit, which errors can occur due to signal propagation delay, the control circuit resets the snoop valid bit only after a preselected internal delay period.

REFERENCES:
patent: 4713755 (1987-12-01), Worley, Jr. et al.
patent: 4959777 (1990-09-01), Holman, Jr.
patent: 4977498 (1990-12-01), Rastegar et al.
patent: 5056002 (1991-10-01), Watanabe
patent: 5067078 (1991-11-01), Talgam et al.
patent: 5072369 (1991-12-01), Theus et al.
patent: 5119485 (1992-06-01), Ledbetter, Jr. et al.
patent: 5146603 (1992-09-01), Frost et al.
patent: 5193170 (1993-03-01), Lam

Affiliated with

Also associated with

Rating

Control circuit for resetting a snoop valid bit in a dual port c does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Control circuit for resetting a snoop valid bit in a dual port c, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Control circuit for resetting a snoop valid bit in a dual port c will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-800713