Control circuit for dual port memory

Details Control circuit for dual port memory Control circuit for dual port memory

1991-04-30

1995-06-27

Baker, Stephen M.

Excavating

G06F 1110

Patent

active

054286328

ABSTRACT:
A memory device provides a control circuit attached to a parity bit position of a memory array. When a selected single bit within an array entry has its value changed without affecting the remaining bits of the entry, the control circuit senses the previous value of the parity bit and internally stores the complement of that value into the parity bit position for that entry. This complementing of the parity bit occurs during the same memory cycle in which the selected bit is changed. Complementing of the parity bit to ensure proper parity function occurs without communication off of the device, and so is completely transparent to the outside world.

REFERENCES:
patent: 4483003 (1984-11-01), Beal
patent: 4843542 (1989-06-01), Dashiell et al.
patent: 4918695 (1990-04-01), Scheuneman
patent: 4920536 (1990-04-01), Hammond
patent: 4977498 (1990-12-01), Rastegar et al.

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