Control circuit for delay locked loop

Details Control circuit for delay locked loop Control circuit for delay locked loop

2006-04-11

2006-04-11

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Utilizing three or more electrode solid-state device

C327S437000, C327S576000

Reexamination Certificate

active

07026859

ABSTRACT:
Provided is directed to a delay locked loop control circuit capable of reducing a test time and preventing a yield from being reduced, by preventing a failure due to a charge sharing and a failure in a specific frequency and voltage due to a noise of a feedback clock, by means of including: a level setting unit for setting an initial level of a locked state signal, which is decided whether or not phases of a reference clock and a feedback clock are aligned; a signal generation unit for generating a third control signal according to a first control signal comparing phases of the reference clock and the feedback clock, and a second control signal checking out phases of the reference clock and the feedback clock in every predetermined time; a level maintaining unit for maintaining a level of the locked state signal according to the locked state signal and a fourth control signal comparing a signal delaying the feedback clock for a predetermined time with the reference clock; a detection unit for varying a level of the locked state signal by detecting whether or not phases of a reference clock and a feedback clock are aligned according to the first to third control signals; and a control unit for controlling a variation of the locked state signal by means of the detection unit according to the fourth control signal.

REFERENCES:
patent: 5304867 (1994-04-01), Morris
patent: 5982218 (1999-11-01), Sugawara
patent: 5986443 (1999-11-01), Jeong
patent: 6346823 (2002-02-01), Kim

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