Boots – shoes – and leggings
Patent
1993-07-14
1996-03-05
Rudolph, Rebecca L.
Boots, shoes, and leggings
395405, 364DIG1, 36518904, 36523003, G06F 1202
Patent
active
054974739
ABSTRACT:
A signal cache memory controller which includes line for inputting an index section of an address is formed with a branch line which is intervened by an address delay circuit. In each of banks X and Y, a switching circuit selects the data which has been delayed in response to a select signal Sse being outputted as a cache-access address to be outputted to a tag memory. An address comparator compares a tag section of the address input through a signal line for inputting the tag section with a reference address output from the tag memory and outputs an coincidence signal if there is a coincidence therebetween. When the coincidence signal is generated and the select signal Sse is not generated, a bank-hit signal generating circuit generated a bank-hit signal Sbh, in response to which a select-signal generating circuit generates the select signal Sse. The circuit for controlling a cache memory which is divided into a plurality of banks enables the writing of data in the cache in every cycle.
REFERENCES:
patent: 5067078 (1991-11-01), Talgam et al.
patent: 5249282 (1993-09-01), Segers
patent: 5353424 (1994-10-01), Partovi et al.
Miyoshi Akira
Yoshioka Shirou
Matsushita Electric - Industrial Co., Ltd.
Nguyen Hiep T.
Rudolph Rebecca L.
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