Control circuit for clock multiplier

Details Control circuit for clock multiplier Control circuit for clock multiplier

1995-05-05

1996-10-08

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

327119, 327356, H03B 1900, G06F 744

Patent

active

055635385

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Technical Field
This invention relates to a control circuit for an output clock of a clock multiplier used for optical transmission equipment and multiplexers in a digital transmission system. More specifically, the invention relates to a control circuit for a clock multiplier capable of controlling the output signal when a multiplied signal is present at the output due to influences of noise while no input clock signal is applied to the input of the clock multiplier.
2. Background Art
A clock multiplier may be required, for example, in a general digital system, when the speed of a main processing unit is set at V/x to get phase margin regarding the processing in a system, in which processing is implemented by the speed V at the input and by the speed V at the output. To output from the system such a signal processed at the speed V/x as a signal with the speed V, data must be converted into data with the speed V on the basis of a clock having the speed V/x used for processing multiplied x times.
A clock multiplier is required in the situation described above. In a conventional clock multiplier, a limiter amplifier is provided in order for restituting a loss occurring when a signal is fed to the input terminal of the clock multiplier, a loss caused by an insertion of a band pass filter, and the like. To sufficiently restitute such losses, a limiter amplifier having a gain of about 32 dB is typically used. However, when the limiter amplifier has a high gain, input of noise may be amplified even if no input signal is applied. Upon amplification of noise, a signal having amplitude and frequency equivalent to the multiplied clock obtainable when an input signal is applied, can be produced at the output terminal.
Though no known publication properly discloses a control circuit for a clock multiplier that controls the output of a multiplier as last mentioned, Japanese Unexamined Patent Publication Sho No. 56-47,139, does disclose control of an output clock. The control circuit shown in this Japanese Patent Publication includes a circuit for detecting signal loss and a gate circuit are inserted between the output of the regenerated clock signal and an output terminal. With the control circuit thus constituted, particularly when a high frequency signal is used as a clock signal, the gate circuit to be inserted is required to have high performance electrical characteristics, representatively, such as rise time. Such a gate circuit, however, is expensive. The number of connection points for a high frequency signal increases in order to insert the gate circuit, thereby inducing waveforms of the clock signal to be impaired.


SUMMARY OF THE INVENTION

It is an object of the invention to provide a control circuit for a clock multiplier which solves problems arising out of conventional clock multipliers and control circuits therefor.
A control circuit for a clock multiplier according to the invention includes a clock multiplier for multiplying an input clock signal. The clock multiplier includes an amplifier for amplifying the multiplied clock signal for producing an amplified, multiplied clock signal at an output of the clock multiplier. A peak detection circuit is provided for detecting an amplitude value of the input clock signal. A comparator for compares the amplitude value detected at the peak detection circuit with a first reference voltage, and a switching means is provided for switching a second reference voltage of the amplifier of the clock multiplier.
The switching mean includes an analog switching circuit controlled by the output of the comparator through an input switching terminal. When the input at the input switching terminal indicates a high level, an open terminal is selected as the input of the analog switching circuit. When the input at the input switching terminal indicates a low level, the switching means selects, as an input of the analog switching circuit, a terminal that is set to the maximum voltage level of the signal fed to the amplifier.
When the input of the

REFERENCES:
patent: 3710253 (1973-01-01), O'Neill
patent: 5291081 (1994-03-01), Takeuchi et al.
patent: 5438245 (1995-08-01), Kii et al.
Tsukuda, A. et al., "2.4 Gb/s Timing Recovery Circuit Module", published in Mar. 1992, Spring Meeting for Electronics, Information and Communication, pp. 4-135.

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