Control circuit for an S-DRAM

Details Control circuit for an S-DRAM Control circuit for an S-DRAM

2003-02-26

2004-04-06

Yoha, Connie C. (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S193000, C365S230080, C365S189120

Reexamination Certificate

active

06717886

ABSTRACT:

BACKGROUND OF INVENTION
The invention relates to a control circuit for the data path of an S-DRAM. RAM modules are standard memory modules for main memory. D-RAM memories comprise large scale integrated transistors and capacitors. In order to maintain the information, the memory content has to be continually refreshed in this case (refresh). A synchronous D-RAM (S-DRAM) permits the memory access without additional waiting cycles. In this case, the data transfer between the S-DRAM and an external data bus is effected synchronously with the external clock signal.
FIG. 1
shows an S-DRAM memory module according to the prior art. The S-DRAM memory module is connected to an external control bus, to an external address bus and to an external data bus. Via command PADS, the control commands present on the external control bus are read in by an integrated command receiver and the reception signals are applied, after having undergone signal amplification, to a command decoder. The command decoder decodes the applied control commands, which have a width of 4 bits, for example, to form internal control commands, such as, for instance, write (WR) and read (RD). The S-DRAM comprises a state machine or a sequence controller which controls the internal sequences in a manner dependent on the decoded internal control commands. The sequence controller is clocked by a clock signal. For this purpose, an external clock signal CLK
ext
is applied to the S-DRAM and signal-amplified by an integrated clock signal receiver. The amplified clock signal is distributed by a clock tree in a tree-like manner in the integrated S-DRAM and passes via an internal clock line to a sequence controller. The external clock signal is furthermore applied to a delay locked loop DLL. The delay locked loop DLL effects a negative phase shift of the external clock signal CLK that is present. The internal DLL clock signal leads the external clock signal in order that the data are present synchronously with the external clock signal at the data pads. The output signal driver OCD (off chip driver) of a data path, said output signal driver being integrated in the S-DRAM, is clocked with the DLL clock signal DLL
CLK
. Connected downstream of the delay locked loop DLL is a propagation time element which forms an internal clock signal (VE-CLK) which is simulated identically to the external clock signal, i.e. VE-CLK is completely synchronous with CLK
ext
. The propagation time element in this respect compensates for the negative phase shift of the delay locked loop DLL.
The internal sequence controller generates control signals for the internal operating sequence of the S-DRAM in a manner dependent on the decoded commands. The sequence controller generates an RAS signal (row address strobe) for driving a row address latch and a CAS signal (column address select) for driving a column address latch. The row address latch and the column address latch are connected to an address signal receiver of the S-DRAM via an internal address bus. The S-DRAM receives an external address via the external address bus at the address PADS, the address signals present being signal-amplified by an address receiver. In order to save terminals, the address is input in two steps in DRAM memories. In a first step, the lower address bits are loaded with the RAS signal into the row address latch. In a second step, the more-significant address bits are loaded with the CAS signal into the column address latch. The address bits are applied to a row and column decoder, respectively, for access to a memory cell within the matrix-type memory cell array. The row address latch and the column address latch and also the row decoder and column decoder together form an address signal decoder. For the refresh of the memory cells, the memory cell array receives a refresh control signal from the sequence controller. A refresh counter, which receives an enable signal from the sequence controller, successively generates all existing row addresses, which are then applied to the address bus. The sequence controller generates an RAS control signal for this purpose. Through the activation of a word line, all the memory cells connected to it are refreshed.
The memory cell array is furthermore connected to read/write amplifiers. The number of read/write amplifiers depends on the memory architecture, the word width and the prefetch. Given prefetch
4
with a word width of 32, by way of example, 128 read/write amplifiers are in operation simultaneously. If four independent memory banks are provided, for example, a total of 512 read/write amplifiers are integrated on the memory chip.
Via the read/write amplifiers, a data bit is in each case written to an addressed memory cell or read from it. The read/write amplifiers are connected to an internal data path of the S-DRAM via an internal data bus. Via the data path, the data present in the external data bus are written to the S-DRAM synchronously and output from the S-DRAM synchronously. The data path is connected to the data PADS of the S-DRAM.
For reading in the data, the data path acquires a data receiver for receiving the data that are present externally. An internal driver circuit for the data to be written (WR driver) carries out a signal amplification of the received data and outputs the read-in data to the read/write amplifiers via the internal bus. The driver circuit WR driver is driven by a write latency generator which is clocked by the internal clock signal VE-CLK. For its part, the write latency generator is connected to a decoder.
For synchronous outputting of data, the data path contains a data FIFO register, downstream of which an output data driver circuit (OCD driver) is connected. The FIFO register is driven by the read/write amplifier by means of an input pointer and by a read latency generator by means of an output pointer or a time-delayed data enable signal. The read latency generator is likewise connected to a decoder.
The two decoders for the read latency generator and the write latency generator are connected via internal control lines to a mode register in which the data for controlling the operating modes within the S-DRAM are stored. The mode register can be initialized by a mode register set command via the internal address bus. The mode register is initialized after the switch-on. Before external control commands are applied to the S-DRAM, the mode register is initialized. The mode register contains control data for the CAS latency, for test modes and for a DLL reset.
The sequence controller generates, in a manner dependent on the external control commands, an internal write command PAW for activating the write latency generator and an internal read command PAR for activating the read latency generator.
FIG. 2
shows a timing diagram for elucidating the method of operation of a conventional S-DRAM. An external clock signal CLK-external is present at the S-DRAM. The state machine or sequence controller generates an internal command signal in a manner dependent on the decoded read command RD. The read command is applied relative to a rising signal edge of the external clock signal CLK
ext
. The clock signal is received and distributed. With the internal clock signal CLK
int
, the command is accepted and subsequently decoded. The sequence controller generates an internal read command control signal PAR
int
, for example.
The internal control signal PAR
int
is generated with a certain signal delay, namely an out-decoding time &Dgr;t
DEK
. This out-decoding time comprises a signal delay on account of the clock signal receiver, on account of the clock signal line tree (clock tree) and on account of signal delays within the sequence controller.
t
DEK
=t
CLK
RECEIVER
+t
CLK
TREE
+t
Latch
+t
CMD
Decode
+t
PAR
GENERATION
The generated internal read signal PAR
int
is applied to the read/write amplifiers with a short signal delay and said amplifiers output the data to be read out to the internal data bus. With a further time delay &Dgr;t
FIFO
the data pass from the internal data bus via

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