Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-09-21
2003-01-07
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185130, C365S185230
Reexamination Certificate
active
06504758
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile memory with hierarchical row decoding, and more in particular to a control circuit of a variable-voltage regulator forming part of said nonvolatile memory.
2. Description of the Related Art
As is known, nonvolatile memory devices are typically organized as an array, in which word lines connect gate terminals of the memory cells arranged on the same row, and bit lines connect drain terminals of the memory cells arranged on the same column.
The rows of the memory array are addressed by means of a row decoder, which receives at an input a coded address, and has the purpose of biasing the word line of the row each time addressed at a stable and precise voltage, the value of which depends upon the type of operation carried out on the memory cells of that particular row (reading, programming, verifying, erasing).
Furthermore, in certain nonvolatile memories the memory array is organized in global word lines and local word lines. In particular, the memory array comprises global word lines and a plurality of local word lines for each global word line, the local word lines being connected to the corresponding global word line via respective switching stages having the purpose of enabling, when they are on, transfer of the voltage present on the global word line to the respective local word line, and to which the memory cells are then physically connected.
A global row decoder addresses the global word lines, and a local row decoder addresses the local word lines. In particular, the global row decoder is directly connected to the global word lines and each time biases the line or lines selected, whilst the local row decoder controls the switching stages in such a way as to enable selective connection between the local word lines and the respective global word line.
For proper operation, each of the switching stages needs to receive a biasing voltage that is stable, precise and variable according to discrete values within a certain range, in which the lower end of the range is less than the supply voltage.
In particular, the switching stages typically have a CMOS-type structure and are formed by a PMOS transistor and an NMOS transistor having their respective source and drain terminals connected together and to the global word line, their respective drain and source terminals connected together and to the local word line, and gate terminals receiving respective control signals that are complementary to one another.
The NMOS transistor moreover has a bulk terminal which must be biased at a voltage that is equal to ground voltage during the steps of reading and programming of the memory cells, and is equal to a negative erasure voltage, for example −8 V, during the erasure step, whilst the PMOS transistor has a bulk terminal which must be biased at a voltage that typically assumes a value of approximately 6 V during the reading step, a voltage of approximately 1.5 V during the erasure step, and presents a staircase waveform with pre-set steps during the programming step, in which the initial and final values of the staircase depend upon the type of memory cells used; for example, for four-level memory cells (i.e., memory cells able to store 2 bits per cell) the programming voltage varies between 1.5 and 9 V with steps of approximately 300 mV.
It is, however, known that nonvolatile memories are typically of the single-supply-voltage type; i.e., they receive from outside a single supply voltage having a value of, for instance, between 2.5 and 3.8 V.
Consequently, the aforesaid voltage variable between 1.5 and 9 V, as in general all voltages that present staircase waveforms, is generated inside the nonvolatile memory in the way illustrated in
FIG. 1
, namely, by means of a supply stage formed by a voltage-boosting circuit
2
and a voltage regulator
3
cascade-connected.
In particular, the voltage-boosting circuit
2
, generally known as “voltage booster” or “charge pump”, is fed with the supply voltage V
CC
supplied from outside to the nonvolatile memory and supplies at output a boosted voltage V
HV
higher than the supply voltage V
CC
. Since the boosted voltage V
HV
is not very voltage-stable, it is then supplied at input to the voltage regulator
3
, which supplies at output a regulated voltage V
REG
, which is voltage-stable and presents the staircase waveform with the values referred to above.
In particular, the voltage regulator
3
typically has a circuit structure of the variable-gain feedback operational amplifier type shown in
FIG. 2
; i.e., it basically comprises an operational amplifier
4
and a resistive-type feedback network
8
.
In detail, the operational amplifier
4
has a supply terminal receiving the boosted voltage V
HV
generated by the voltage-boosting circuit
2
, a non-inverting terminal receiving a reference voltage V
REF
, an inverting terminal connected to a node
6
, and an output terminal supplying the regulated voltage V
REG
, whilst the feedback network
8
consists of a resistive divider formed by a first feedback resistor
10
of a variable type connected between the output terminal of the operational amplifier
4
and the node
6
and having a resistance R
A
, and a second feedback resistor
12
connected between the node
6
and the inverting terminal of the operational amplifier
4
and having a resistance R
B
.
With the circuit structure shown in
FIG. 2
, the regulated voltage V
REG
is therefore linked to the reference voltage V
REF
by the known relation:
V
REG
=
V
REF
·
(
1
+
R
A
R
B
)
Given that the second feedback resistor
12
has a constant resistance R
B
, by varying the resistance R
A
of the first feedback resistor
10
, the regulated voltage V
REG
is accordingly made to vary as a function of the ratio between the feedback resistances R
A
and R
B
.
The first feedback resistor
10
is generally made in the way shown in Figure namely, it is formed by N resistors, designated by
14
.
1
,
14
.
2
, . . . ,
14
.N, connected in series and identical to one another, and a plurality of switches, designated by
16
.
1
,
16
.
2
, . . . ,
16
.N, each of which is connected in parallel to a respective resistor
14
.
1
-
14
.N, and by means of which it is possible to short-circuit each of the resistors
14
.
1
-
14
.N independently of one another.
The switches
16
.
1
-
16
.N are typically pass-gate CMOS switches, and each of them receives, on a first control terminal and a second control terminal, respectively a first control signal and a second control signal, which are complementary to one another and are designated, in
FIG. 3
, by &phgr;
1
, {overscore (&phgr;)}
1
for the first switch
16
.
1
, &phgr;
2
, {overscore (&phgr;)}
2
for the second switch
16
.
2
, and so forth.
In particular, through the appropriate opening or closing command of the switches
16
.
1
-
16
.N it is possible to obtain a resistance that varies between a minimum value of zero, when all the switches
16
.
1
-
16
.N receive a closing command and short-circuit the respective resistors
14
.
1
-
14
.N, and a maximum value equal to the sum of the resistances of all the resistors
14
.
1
-
14
.N, when all the switches
16
.
1
-
16
.N receive an opening command and do not short-circuit the respective resistors.
The smaller the resistance of the switches
16
.
1
-
16
.N that are closed, the greater the precision obtained on the regulated voltage V
REG
,.
In fact, if it is assumed that of the N resistors
14
.
1
-
14
.N that form the first feedback resistor
10
, K are not short-circuited, i.e., that is K switches are open and N-K switches are closed, then the ideal regulated voltage V
REG
, i.e., the voltage that would be obtained if all the switches were ideal and hence did not have a resistance of their own, would be:
V
REG
=
V
REF
·
(
1
+
K
·
R
S
R
B
)
where R
S
is the resistance of each of the resistors
14
.
1
-
14
.N, whereas the actual regulated voltage V
REG
, i.e., the voltage that is obtained if the resistance of the switches i
Khouri Osama
Micheloni Rino
Sacco Andrea
Torelli Guido
Bennett II Harold H.
Jorgenson Lisa K.
Mai Son
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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