Control circuit for a memory array

Details Control circuit for a memory array Control circuit for a memory array

1988-02-01

1989-05-16

Chin, Tommy P.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358 11, 358160, H04N 701

Patent

active

048314420

ABSTRACT:
A control circuit includes a data reduction decoder and an interpolating filter, the data reduction decoder having an line memory for the video signal included in a scanning line. The interpolating filter cooperates with the line memory and includes a first adder, a subtracter, a first and a second multiplier, and a second adder. The control circuit controls the writing of digital signals of a field corresponding to any of the conventional television standards into a memory array and the readout of digital signals at an increased field rate, preferably at twice the field rate.

REFERENCES:
patent: 3898378 (1975-08-01), Hinoshita et al.
patent: 4041531 (1977-08-01), Bingham
patent: 4558347 (1985-12-01), Pritchard
"Design of a DPCM Codec for VLSI Realization in CMOS Technology", Proceedings of the IEEE, vol. 73, No. 4, Apr. 1985, by Peter Pirsch, pp. 592 through 598.
Elektrisches Nachrichtenwesen, "Videocodec fur die Breitbandubertragung", by P. Pirsch, 10/8/84, pp. 447 through 449.
"Applications of Picture Memories in Television Receivers", IEEE Transactions on Consumer Electronics, vol. CE-29, No. 3, 8/83, by Berkhoff, Kraus & Raven, 251-258.
"Composite Television Coding: Subsampling & Interpolation", S.M.P.T.E. Journal, vol. 91, No. 8, Aug. 1982, by Brainard, Netravali & Pearson, pp. 717-724.

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