Static information storage and retrieval – Read only systems – Semiconductive
Reexamination Certificate
2001-04-13
2002-08-27
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read only systems
Semiconductive
C365S185230, C365S230060, C365S230080
Reexamination Certificate
active
06442058
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a control circuit used in a microcomputer, a semiconductor memory, or the like as a command processor, and a semiconductor device including the same. More particularly, the present invention relates to a control circuit having an internal code interpretation section, which is used in a non-volatile semiconductor memory requiring a complicated internal control, and a semiconductor device including the same.
2. Description of the Related Art
Recent advances of semiconductor technology and increasing variety of its applications lead to further complication and diversification of the specification of a microcomputer, a semiconductor memory, and the like. The development of a high-performance, highly-reliable device in a short time is a challenge. To address such a challenge, a circuit block in an existing device is preferably reused so as to reduce the development time. Particularly, since a typical control circuit is a collection of complicated circuits, the reuse of an existing circuit significantly contributes to a reduction in the development time.
A control circuit having an internal code interpretation section may be used for a non-volatile semiconductor memory or the like requiring complicated internal control. An internal command which can be executed directly by a control circuit is herein referred to as an “internal command”. A command, which externally instructs a semiconductor memory or the like to operate, is referred to as an “external command”. Typically, an operation specified by an external command is achieved by a number of internal commands which are executed in a specified sequence. Such a group of internal commands which are arranged in a specified order (a program composed of internal commands so as to achieve an operation specified by an internal command) is herein referred to as an “internal code”.
A semiconductor memory will be described as an example. An external instruction to a semiconductor memory, such as data write and data erase, corresponds to an external command. A series of internal commands included in a semiconductor memory, which are sequentially executed so as to achieve data write or data erase, corresponds to an internal code. In particular, the area of a semiconductor memory or the like should be as small as possible. Therefore, a control circuit including internal commands having a fixed instruction length, which leads to simplification of the circuit, is used.
FIG. 11
is a diagram showing a structure of a conventional control circuit
210
. The control circuit
210
includes an external command register
26
, a control signal register
27
, and an internal code interpretation section
29
. An external command
2
B input from the outside of the control circuit
210
is stored in the external command register
26
. The control signal register
27
receives a signal
2
I output from the internal code interpretation section
29
, and outputs a control signal
2
A to the outside of the control circuit
210
. The internal code interpretation section
29
includes an internal code storage section
21
, an internal command register
22
, a program counter
23
, an internal command execution section
24
, and an external command recognition section
25
. The internal code storage section
21
(hereinafter referred to as an “internal ROM”) includes a ROM or the like in which an internal code is stored. The internal ROM
21
may include a non-volatile memory. The internal command register
22
is used to store an internal command
2
E read from the internal ROM
21
, and outputs an internal command
2
F. The program counter
23
selects and provides the address of an internal command to be executed, from the addresses of a plurality of internal commands stored in the internal ROM
21
. The internal command execution
24
executes the internal command
2
F output from the internal command register
22
. The external command recognition section
25
recognizes an operation instructed by an external command.
FIG. 12
is a diagram showing a structure of a semiconductor memory
220
including the control circuit
210
. The semiconductor memory
220
includes an input/output buffer
201
, an input buffer
202
, an internal booster circuit
203
, a write/erase control circuit
204
, and address decoder circuit
205
, a memory array
206
, a sense circuit
207
, and a control circuit
210
. The input/output buffer
201
has data buses D
0
through Dn at the input and output sides. The data buses D
0
through Dn are used to input external commands, write data, and the like, and to output read data. The input buffer
202
has address buses A
0
through An at the input side. The input buffer
202
receives a chip selection signal CE# (# represents an inverted signal) and a command write enable signal WE#. The internal booster circuit
203
boosts a supply voltage Vpp. The memory array
206
is used to store information. The sense circuit
207
reads out information from the memory array
206
.
In the semiconductor memory
220
, the circuits
203
,
204
and
207
are controlled in accordance with the control signal
2
A output from the control circuit
210
so that information is written to or erased from the memory array
206
. The control signal
2
A is input to the internal booster circuit
203
, the write/erase control circuit
204
and the sense circuit
207
. For example, the internal booster circuit
203
is controlled so that the start or end of a boost is controlled in accordance with the control signal
2
A, or the boosted potential of the supply voltage Vpp is determined.
An operation of the control circuit
210
will be described.
The external command
2
B stored in the external command register
26
is output from the external command register
26
to the external command recognition section
25
. The external command recognition section
25
recognizes whether the external command
2
B can be executed by the control circuit
210
. When it is determined that the external command
2
B can be executed by the control circuit
210
, the external command recognition section
25
outputs a leading address
2
C of an internal code required for an operation specified by the external command
2
B. The program counter
23
selects and provides the address of an internal command to be executed, from a plurality of internal command addresses stored in the internal ROM
21
. The internal ROM
21
outputs an internal command corresponding to a leading address
2
D of the internal code stored in the program counter
23
(in this case, the address
2
D is identical to the address
2
C), i.e., a leading internal command
2
E in the internal code to be executed, to the internal command register
22
in which the internal command is in turn stored. The internal command execution section
24
executes a specified operation, control, or the like in accordance with an internal command
2
F output from the internal command register
22
. The internal command execution section
24
outputs a signal
2
I to update a value stored in the control signal register
27
if required, or outputs an address
2
G of an internal command to be executed to the program counter
23
in order to store an internal code
2
E to be executed in the internal command register
22
.
As described above, the control circuit
210
achieves an operation specified by the external command
2
B by a plurality of internal commands stored in the internal ROM
21
being output to the internal command execution section
24
in a specified sequence, and being executed sequentially.
In the control circuit
210
, the implementation of a new external code, the change of an existing external code, and the like can be achieved by changing an internal code stored in the internal ROM
21
. Therefore, the control circuit
210
is used for general purposes.
When a semiconductor memory having a new operating specification is developed, the configuration of the control circuit of the semiconductor memory is used, as
Le Vu A.
Morrison & Foerster / LLP
Nguyen Van-Thu
Sharp Kabushiki Kaisha
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