Control apparatus for controlling data read accesses to memory a

Details Control apparatus for controlling data read accesses to memory a Control apparatus for controlling data read accesses to memory a

1994-02-23

1996-11-26

Kim, Matthew M.

395403, G06F 1202

Patent

active

055795005

ABSTRACT:
An apparatus and method for controlling data read access to memory, in response to an access request sent through a system bus. The apparatus includes an data storage device for preserving data corresponding to a predetermined address; a judging device for judging whether an access address indicated by the access request matches the predetermined address; and a control device for making the data storage device output data preserved therein to the system bus when the access address has been judged to match the predetermined address, and for making the data storage device hold data corresponding to a next address subsequent to the access address when the access address has been judged not to match the predetermined address.

REFERENCES:
patent: 4691277 (1987-09-01), Kronstadt et al.
patent: 4872138 (1989-10-01), Ciacci
patent: 4914575 (1990-04-01), Kihara et al.
patent: 5157776 (1992-10-01), Foster
IBM Technical Disclosure Bulleting, vol. 31, No. 3, Aug. 1988, New York, pp. 303-306, `High performance microprocessor memory system`.

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