Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Patent
1995-06-06
1997-09-02
Gaffin, Jeffrey A.
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
341122, 341123, 341162, H03M 112
Patent
active
056637292
ABSTRACT:
The AD conversion control section of the processor sets the clock generating circuit of the output port alternately to an L-level output condition and an H-level output condition to generate a clock signal. A chip select signal is caused to be output from the chip select circuit of the output port in synchronization with output of the first clock signal by the interruption signal. Furthermore, the bit data output in series bit by bit from the AD converter in synchronization with occurrence of a clock signal is incorporated bit by bit in synchronization with the interruption signal from the input ports to be stored in the register.
REFERENCES:
patent: 3883863 (1975-05-01), Willard
patent: 4817040 (1989-03-01), Bodley-Scott
patent: 5043911 (1991-08-01), Rashid
patent: 5081454 (1992-01-01), Campbell, Jr. et al.
patent: 5260705 (1993-11-01), Inukai
patent: 5264850 (1993-11-01), Khorram
Takuma Akira
Wada Yoshimi
Fujitsu Limited
Gaffin Jeffrey A.
Kost Jason L. W.
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