Continuously variable clock delay circuit

Details Continuously variable clock delay circuit Continuously variable clock delay circuit

1988-03-25

1989-02-28

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

328 55, 328160, 328 63, 307262, 307529, 307490, 307269, H03K 15135, H03K 1726, G06G 720

Patent

active

048089362

ABSTRACT:
A clock-delay circuit for a sinusoidal clock output includes a pair of current amplifiers, each connected to the clock output, wherein one of the amplifiers generates an amplified signal in phase with the clock output and the other generates a signal shifted in phase by 90.degree.. Both signals are multiplied by control signals to alter their respective amplitudes prior to summation of both multiplier outputs. The sum of the multiplier outputs will be a sinusoidal waveform whose phase depends upon the control currents in the multipliers which are set by the user. Thus, the circuit provides a user-controlled continuously variable delay for a sinusoidal clock.

REFERENCES:
patent: 3475626 (1969-10-01), Holzman et al.
patent: 3675137 (1972-07-01), Raphael
patent: 4039930 (1977-08-01), Lukas
patent: 4041533 (1977-08-01), Yamamoto et al.

Affiliated with

Also associated with

Rating

Continuously variable clock delay circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Continuously variable clock delay circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Continuously variable clock delay circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1370914