Continuous-time differential amplifier with low offset voltage

Details Continuous-time differential amplifier with low offset voltage Continuous-time differential amplifier with low offset voltage

1992-06-01

1993-06-15

Mullins, James B.

Amplifiers

With semiconductor amplifying device

Including differential amplifier

323313, 330257, 330261, H03F 345

Patent

active

052202887

ABSTRACT:
A continuous-time differential amplifier (52, 100) preserves fast settling time while reducing a relatively-high offset voltage-normally associated with a continuous-time differential amplifier using MOS load transistors. The differential amplifier (52, 100) includes a first transistor (81) biased as a current source to provide current into emitters of second (82) and third (83) emitter-coupled input transistors. Fourth (84) and fifth (85) load transistors are respectively coupled between collectors of the second (82) and third (83) input transistors and a power supply voltage terminal. An amplifier (70) having a positive input terminal coupled to the collector of the second input transistor (82) and a negative input terminal receiving a bias voltage biases the control electrodes of the load transistors (84, 85). The amplifier (70) increases the effective transconductance of the load transistors (84, 85) to allow larger control electrode areas, which reduces the effect of transistor mismatch.

REFERENCES:
patent: 4360785 (1982-11-01), Schade, Jr.
patent: 4542348 (1985-09-01), Lucas et al.
patent: 4555670 (1985-11-01), Tanaka
patent: 4583009 (1986-04-01), Eng, Jr.
patent: 4598215 (1986-07-01), Schechtman et al.
patent: 4739281 (1988-04-01), Doyle
Vittoz, Eric A., "MOS Transistors Operated in the Lateral Bipolar Mode and Their Application in CMOS Technology," IEEE Journal of Solid State Circuit, vol. SC-18, No. 3, Jun. 1983.

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