Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2001-06-04
2002-05-28
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S155000
Reexamination Certificate
active
06396428
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates to analog-to-digital converters (ADCs).
BACKGROUND OF THE DISCLOSURE
Continuous time Bandpass Delta Sigma (&Dgr;&Sgr;) modulators are used in ADC systems for digitizing signals of wide dynamic range, e.g., 14 to 16 effective bits in a wide information bandwidth, e.g. 60-100 MHz centering at an IF frequency. Bandpass Delta Sigma modulators typically include a loop filter (also called a resonator for the bandpass modulator), a single bit or multi-bit quantizer, and a single bit or multi-bit feedback digital-to-analog converter (DAC). The loop filter structure can be a sampled-data discrete time filter or a continuous time filter. The discrete time filter is typically implemented in CMOS switched-capacitor technology that has relatively low signal bandwidth. The continuous time loop filter can be implemented in advanced bipolar technology that allows much higher amplifier bandwidth, faster settling and permits the complete modulator to sample at a higher clock rate. This in turn leads to wider signal bandwidth and superior dynamic performance.
A basic second order continuous time bandpass &Dgr;&Sgr; modulator ADC topology is described in “A 3.2 GHz Second-Order Delta-Sigma Modulator Implemented in InP HBT Technology,” Jensen et al, IEEE J. Solid State Circuits, October 1995. The topology has a cascade of two integrators in series in a resonator configuration that drives a one bit comparator-DAC feedback. This topology does not have any compensation for delay in the loop. To achieve greater ADC dynamic range, this topology can be extended into a higher order &Dgr;&Sgr; modulator loop by cascading more of the same second order resonator loops. However this topology suffers from additional unnecessary delay in the signal path because of having all integrators cascading together in series, i.e., a 6
th
order modulator would have 6 integrators in series. Excess delay impacts stability in a high order modulator structure.
A feedforward signal compensation method is described in “An Eighth-Order Bandpass &Dgr;&Sgr; Modulator for A/D Conversion in Digital Radio,” Louis et al, IEEE J. Solid State Circuits, April 1999. The compensation method is applied to a sampled-data resonator (not a continuous time resonator) structure with all switched-capacitor integrators configured in cascade. This sampled data resonator structure has limited frequency bandwidth and is not preferred for digitizing wideband signal at greater than 100 MHz IF frequencies in today's process technologies. This structure also suffers from similar delay issues as discussed above.
SUMMARY OF THE DISCLOSURE
A continuous time Bandpass Delta Sigma (&Dgr;&Sgr;) Modulator architecture with feedforward and feedback coefficients to completely specify both the signal transfer function (STF) and the noise transfer function (NTF) for a stable modulator ADC system is described. In an exemplary embodiment, the structure is capable of implementing any desirable noise shaping response for maximum dynamic range and producing optimal signal transmission response.
In an exemplary embodiment, the new architecture introduces an optimal number of feedforward elements to completely specify the frequency response of the modulator's signal transfer function (STF), hence producing any specified gain flatness and/or phase linearity. Without STF optimization from the feedforward technique, a general modulator topology suffers from much undesired gain variation, e.g., >10 dB may be observed across the signal bandwidth of interest, resulting in necessary gain correction in the digital signal processing (DSP) backend. A compensation technique in accordance with an aspect of the invention corrects for the inherent error in a general &Dgr;&Sgr; architecture and potentially reduces overall system complexity in subsequent DSP hardware.
In an exemplary embodiment, the topology configures the second integrator in a second order modulator in a local feedback such that only half as many integrators are in the forward signal path. An excess delay compensation technique can be integrated with the feedforward compensation technique.
REFERENCES:
patent: 5274375 (1993-12-01), Thompson
patent: 5351050 (1994-09-01), Thompson et al.
patent: 5682161 (1997-10-01), Ribner et al.
patent: 5793811 (1998-08-01), Yu
patent: 6028544 (2000-02-01), Zarubinsky et al.
patent: 6249237 (2001-07-01), Prater
IEEE Journal of Solid-State Circuits, An Eighth-Order Bandpass Delta Sigma Modulator for A/D Conversion in Digital Radio by Loai Louis, John Abeaarius, and Gordon W. Roberts, Member, IEEE, vol. 34, No. 4, Apr. 1999, pp. 423-431.
IEEE Journal of Solid-State Circuits, A 3.2 GHz Second-Order Delta-Sigma Modulator Implemented in InP HBT Technology, vol. 30, No. 10, Oct. 1995, pp. 1119-1126.
Alkov Leonard A.
Lenzen, Jr. Glenn H.
Young Brian
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